An approach to parallel architecture modelling (abstract only)

Traditionally, two kinds of models - analytical and discrete-event simulator - have been used for functional modeling of multiple-microprocessor architectures (1,2). Given the complexity of design emanating from interactions among various components of such architectures - both hardware and software - useful models of such systems are very difficult to build.

Analytical models that are used for modeling such architectures are mostly queue networks (3). When such queue networks are used for system modeling, often product-form solutions are not easy to obtain; in such cases, approximate method in the form of hierarchical decomposition or operational analysis (4,5) is adopted to arrive at a particular solution. The results obtained from such analysis may not give the desired degree of accuracy in all such cases.

Discrete-event simulation technique can be employed to investigate design alternatives at various stages of design. As such, the degree of detail in a typical such simulator varies - simulation can be performed at behavioral, instruction or at hardware-description level. For a typically involved simulator construction however, often the cost and the complexity of simulator design approach that of the system to be modeled.

Further, run-time resource requirement, provisions for static and dynamic reconfiguration and flexibility for experimentation at different levels provide additional constraints for such simulator design. An incremental design methodology based on a modified access-graph technique (6,7) could be the most ideal approach for such a reconfigurable simulator design (8).

The basic components of an access-graph as considered in the present work, are of three types: Process, Monitor, and nodal micro. A process can send or retrieve data from a nodal micro or monitor. Also two processes can communicate with each other through monitors only. Mutual exclusion in monitors has been enforced to ensure that only one process can get access to a monitor at any instant of time. For avoiding deadlock and other undesirable situations, provisions also exist to continue or suspend a process. Starting with a simple source-to-destination message transfer scheme the software components of the simulator are derived in an incremental fashion with the help of such access-graphs through several iterations.

The basic structure of the reconfigurable simulator consists of two main parts: resource management and massage communication So, to start with, an access-graph for a message transfer from a single source to a single destination micro (figure 1) node should contain a source process, a communication process and a destination process. Resource management involves only two buffers: i) an input buffer, to which the source process transfers data from the source node and from which the communicator process consumers data and ii) an output buffer to which the communicator process transfers data and from which, the data is consumed by the destination process.

In the next stage of decomposition, multiple source and destination processes can be introduced in the access-graph, as message-transfer mechanism involves more than one source and destination nodes. Separate i/o local buffers, for each source and destination processes can also be introduced for ease of message communication. A further decomposition could follow from the fact that messages could be sent from local input to local output buffers through common global buffers, each of which can act as a separate buffer monitor. Such transfer could be done by a pair of identical processes, which act on common i/o buffers and global buffers, at both source and destination ends. The refinement can be continued in this manner.

Following the design principle of keeping the structure of the simulator simple, together with other well-known s/w design techniques like information-hiding and top-down design, the final structure of the message-passing modules of the generic simulator can be arrived at by this incremental access-graph modification scheme. The salient feature of such access-graph analysis, as outlined above, is the ability to clearly analyze and decompose the message-transfer mechanism into separate, non-overlapping functional modules.