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LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing

Published: 15 July 2018 Publication History

Abstract

LEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC.

References

[1]
ITRS, International Technology Roadmap for Semiconductors 2.0: 2015 Edition, ITRS, 2015.
[2]
W. Van Heddeghem, S. Lambert, B. Lannoo, D. Colle, M. Pickavet y P. Demeester, «Trends in Worldwide ICT Electricity Consumption from 2007 to 2012,» Comput. Commun., vol. 50, pp. 64--76, 9 2014.
[3]
R. Griessl y e. al, «A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters,» de 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014.
[4]
A. Duran, E. Ayguadé, R. M. Badia, J. Labarta, L. Martinell, X. Martorell y J. Planas, «Ompss: a Proposal for Programming Heterogeneous Multi-Core Architectures.,» vol. 21, pp. 173--193, 6 2011.
[5]
M. Pericàs, «ξ-TAO: A Cache-centric Execution Model and Runtime for Deep Parallel Multicore Topologies,» de Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, NY, USA, 2016.
[6]
A. Oleksiak y e. al, «M2DC - Modular Microserver DataCentre with heterogeneous hardware,» Microprocessors and Microsystems, vol. 52, pp. 117--130, 2017.
[7]
O. Port y Y. Etsion, «DFiant: A dataflow hardware description language,» de 2017 27th International Conference on Field Programmable Logic and Applications (FPL), 2017.
[8]
Xilinx, Vivado High Level Synthesis User Guide, 2015.
[9]
R. Nikhil, «Bluespec System Verilog: efficient, correct RTL from high level specifications,» de Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Proceedings. Second ACM and IEEE International Conference on, 2004.
[10]
J. Bachrach y e. al, «Chisel: Constructing hardware in a Scala embedded language,» de DAC Design Automation Conference 2012, 2012.
[11]
I. Sutherland, «The Tyranny of the Clock,» Commun. ACM, vol. 55, pp. 35--36, 10 2012.
[12]
M. Pericàs, «Elastic Places: An Adaptive Resource Manager for Scalable and Portable Performance,» ACM Trans. Archit. Code Optim., vol. 15, pp. 19:1--19:26, 5 2018.
[13]
H. Rohlin, «Performance-targeted Resource-aware TaskScheduling for Heterogeneous Platforms,» 2018.
[14]
S. Yang, P. Luo, C. C. Loy y X. Tang, «WIDER FACE: A Face Detection Benchmark,» de IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 2016.
[15]
F. Schroff, D. Kalenichenko y J. Philbin, «FaceNet: A Unified Embedding for Face Recognition and Clustering,» CoRR, vol. abs/1503.03832, 2015.
[16]
F. Pedregosa y e. al, «Scikit-learn: Machine Learning in Python,» CoRR, vol. abs/1201.0490, 2012.
[17]
D. Amodei y e. al, «Deep Speech 2 : End-to-End Speech Recognition in English and Mandarin,» de Proceedings of The 33rd International Conference on Machine Learning, New York, New York, USA, 2016.
[18]
J. Redmon y A. Farhadi, «YOLO9000: Better, Faster, Stronger,» CoRR, vol. abs/1612.08242, 2016.
[19]
A. Neumann y e. al, «"KogniChef": A Cognitive Cooking Assistant,» KI - Künstliche Intelligenz, vol. 31, pp. 273--281, 2017.
[20]
A. Bakuli, F. Klawonn, A. Karch y R. Mikolajczyk, «Effects of pathogen dependency in a multi-pathogen infectious disease system including population level heterogeneity - a simulation study,» Theoretical Biology and Medical Modelling, vol. 14, p. 26, 13 12 2017.
[21]
F. Klawonn, T. Wüstefeld y L. Zender, «Statistical Modelling for Data from Experiments with Short Hairpin RNAs,» de Advances in Intelligent Data Analysis IX, Berlin, 2010.

Cited By

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  • (2020)Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware MarginsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2020.298981320:2(341-350)Online publication date: Jun-2020
  • (2020)An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN48063.2020.00032(138-149)Online publication date: Jun-2020
  • (2019)Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS.2019.8854386(129-134)Online publication date: Jul-2019
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cover image ACM Other conferences
SAMOS '18: Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
July 2018
263 pages
ISBN:9781450364942
DOI:10.1145/3229631
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 15 July 2018

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SAMOS XVIII
SAMOS XVIII: Architectures, Modeling, and Simulation
July 15 - 19, 2018
Pythagorion, Greece

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Cited By

View all
  • (2020)Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware MarginsIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2020.298981320:2(341-350)Online publication date: Jun-2020
  • (2020)An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration2020 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)10.1109/DSN48063.2020.00032(138-149)Online publication date: Jun-2020
  • (2019)Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS)10.1109/IOLTS.2019.8854386(129-134)Online publication date: Jul-2019
  • (2019)Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Undervolting Faults2019 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/EMPDP.2019.8671543(242-246)Online publication date: Feb-2019
  • (2018)Comprehensive evaluation of supply voltage underscaling in FPGA on-chip memoriesProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00064(724-736)Online publication date: 20-Oct-2018

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