research-article

Unlocking Fine-Grain Parallelism for AIG Rewriting

Authors:

Vinicius Possan,

Alan Mishchenko,

Keshav Pingali,

Andre ReisAuthors Info & Claims

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Pages 1 - 8

https://doi.org/10.1145/3240765.3240861

Published: 05 November 2018 Publication History

Abstract

Parallel computing is a trend to enhance scalability of electronic design automation (EDA) tools using widely available multicore platforms. In order to benefit from parallelism, well-known EDA algorithms have to be reformulated and optimized for multicore implementation. This paper introduces a set of principles to enable a fine-grain parallel AND-inverter graph (AIG) rewriting. It presents a novel method to discover and rewrite in parallel parts of the AIG, without the need for graph partitioning. Experiments show that, when synthesizing large designs composed of millions of AIG nodes, the parallel rewriting on 40 physical cores is up to 36x and 68x faster than ABC commands rewrite −l and drw, respectively, with comparable quality of results in terms of AIG size and depth.

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Cited By

Cai YYang ZNi LXie BLi X(2024)Enhancing ASIC Technology Mapping via Parallel Supergate Computing2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617589(289-294)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617589
Liu TChen LLi XYuan MYoung E(2024)FineMap: A Fine-grained GPU-parallel LUT Mapping Engine2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473941(392-397)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473941
Li LLi RHa Y(2023)A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325174142:11(3972-3984)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3251741
Show More Cited By

Index Terms

Unlocking Fine-Grain Parallelism for AIG Rewriting
1. Computing methodologies
  1. Parallel computing methodologies
2. Hardware

Index terms have been assigned to the content through auto-classification.

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cover image Guide Proceedings

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Nov 2018

939 pages

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IEEE Press

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Published: 05 November 2018

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Cited By

Cai YYang ZNi LXie BLi X(2024)Enhancing ASIC Technology Mapping via Parallel Supergate Computing2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617589(289-294)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617589
Liu TChen LLi XYuan MYoung E(2024)FineMap: A Fine-grained GPU-parallel LUT Mapping Engine2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473941(392-397)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473941
Li LLi RHa Y(2023)A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.325174142:11(3972-3984)Online publication date: Nov-2023
https://doi.org/10.1109/TCAD.2023.3251741
Li XChen LZhang JWen SSheng WHuang YYuan M(2023)EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323902(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323902
Liu TYoung E(2023)Rethinking AIG Resynthesis in Parallel2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247961(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247961
Berndt AMeinhardt CReis AButzen P(2022)Optimizing machine learning logic circuits with constant signal propagationIntegration, the VLSI Journal10.1016/j.vlsi.2022.08.00487:C(293-305)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1016/j.vlsi.2022.08.004
Berndt AMeinhardt CReis AButzen P(2021)Exploring Constant Signal Propagation to Optimize Neural Network Circuits2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI53441.2021.9529971(1-6)Online publication date: 23-Aug-2021
https://doi.org/10.1109/SBCCI53441.2021.9529971
Ataei SHua WYang YManohar RLu YHe JMaleki SPingali K(2021)An Open-Source EDA Flow for Asynchronous LogicIEEE Design & Test10.1109/MDAT.2021.305133438:2(27-37)Online publication date: Apr-2021
https://doi.org/10.1109/MDAT.2021.3051334

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