Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/3316781.3317901acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros

Published: 02 June 2019 Publication History

Abstract

The mixed-size placement becomes a great challenge in the modern VLSI design. To handle this problem, the three-stage mixed-size placement methodology is considered as the most suitable approach for a commercial design flow, where the placement prototyping is the most important stage. Since standard cells and macros have to be considered simultaneously in this stage, it is more complicated than the other two stages. To reduce complexity and improve design quality, this paper applies the multilevel framework with a design hierarchy-guided clustering scheme for getting a better coarsening result in order to improve outcome in the following stages. We propose an efficient and effective clustering scheme to group standard cells and macros based on the tree built from their design hierarchies. More importantly, our clustering algorithm considers indirect connectivity between macros which is ignored by previous works. Moreover, we propose a new overlapping bounding box constraint to avoid clustering improper macros which have connections to fixed pins. The experimental results show that wirelength and routability are improved by our methodology.

References

[1]
C. Alpert, A. Kahng, G.-J. Nam, S. Reda, and P. Villarrubia, "A semi-persistent clustering technique for VLSI circuit placement," in Proc. of ISPD, pp. 200--207, 2005.
[2]
Y. Cheon and D. F. Wong, "Design hierarchy-guided multilevel circuit partitioning," IEEE Tran. of TCAD, vol. 22, no. 4, pp. 420--427, 2003.
[3]
T.-C. Chen, Y.-W. Chang, and S.-C. Lin, "IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs," in Proc. of ICCAD, pp. 159--164, 2005.
[4]
T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "NTUplace3: An analytical placer for large-scale mixed-size designs with pre-placed blocks and density constraints," IEEE Tran. of TCAD, vol. 27, no. 7, pp. 1228--1240, July 2008.
[5]
T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and T.-Y. Liu, "MP-trees: A packing-based macro placement algorithm for modern mixed-size designs," IEEE Tran. of TCAD, vol. 27, no. 9, pp. 1621--1634, September 2008.
[6]
Y.-L. Chuang, G.-J. Nam, C. J. Alpert, Y.-W. Chang, J. Roy, and N. Viswanathan, "Design-hierarchy aware mixed-size placement for routability optimization," in Proc. of ICCAD, pp. 663--668, 2010.
[7]
Y.-F. Chen, C.-C. Huang, C.-H. Chiou, Y.-W. Chang, and C.-J. Wang, "Routability-driven blockage-aware macro placement," in Proc. of DAC, pp. 1--6, 2014.
[8]
C.-H. Chang, Y.-W. Chang, and T.-C. Chen, "A novel damped-wave framework for macro placement," in Proc. of ICCAD, pp. 504--511, 2017.
[9]
M.-K. Hsu and Y.-W. Chang, "Unified analytical global placement for large-scale mixed-size circuit designs," IEEE Tran. of TCAD, vol. 31, no. 9, pp. 1366--1378, September 2012.
[10]
M.-K. Hsu, Y.-F. Chen, C.-C. Huang, S. Chou, T.-H. Lin, T.-C. Chen, and Y.-W. Chang, "NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs," IEEE Tran. of TCAD, vol. 33, no. 12, pp. 1914--1927, 2014.
[11]
G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: applications in VLSI domain," IEEE Tran. of TVLSI, vol. 7, no. 1, pp. 69--79, March 1999.
[12]
G. Karypis and V Kumar, "Multilevel k-way hypergraph partitioning," in Proc. of DAC, pp. 343--348, 1999.
[13]
M. Kuwano and Y. Takashima, "Stable-LSE based analytical placement with overlap removable length," in Proc. of SASIMI, pp. 115--120, 2010.
[14]
J.-M. Lin, Y.-L. Deng, S.-T. Li, B.-H. Yu, L.-Y. Chang, and T.-W. Peng, "Regularity-aware routability-driven macro placement methodology for mixed-size circuits with obstacles," IEEE Tran. of TVLSI, 2018.
[15]
W. C. Naylor, R. Donelly and L. Sha, "Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer," U.S. Patent 6 301 693 B1, December 16, 1998.
[16]
Himax Technologies, Inc. About Himax. Accessed: August 24, 2018. {Online}. Available: http://www.himax.com.tw/company/about-himax/
[17]
Synopsys, Inc. IC Compiler. Accessed: October 15, 2018. {Online}. Available: https://www.synopsys.com/implementation-and-signoff/physical-implementation/ic-compiler.html

Cited By

View all
  • (2024) Hier-RTLMP : A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334628443:5(1552-1565)Online publication date: May-2024
  • (2023)SRAM Compilation and Placement Co-Optimization for Memory SubsystemsElectronics10.3390/electronics1206135312:6(1353)Online publication date: 12-Mar-2023
  • (2023)An Effective Macro Placement Algorithm Based On Curiosity-Driven Reinforcement Learning2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218370(364-368)Online publication date: 8-May-2023
  • Show More Cited By

Index Terms

  1. Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
    June 2019
    1378 pages
    ISBN:9781450367257
    DOI:10.1145/3316781
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    In-Cooperation

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 02 June 2019

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. clustering
    2. design hierarchy
    3. indirect connectivity
    4. macro placement

    Qualifiers

    • Research-article
    • Research
    • Refereed limited

    Conference

    DAC '19
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

    Upcoming Conference

    DAC '25
    62nd ACM/IEEE Design Automation Conference
    June 22 - 26, 2025
    San Francisco , CA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)34
    • Downloads (Last 6 weeks)4
    Reflects downloads up to 18 Aug 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2024) Hier-RTLMP : A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334628443:5(1552-1565)Online publication date: May-2024
    • (2023)SRAM Compilation and Placement Co-Optimization for Memory SubsystemsElectronics10.3390/electronics1206135312:6(1353)Online publication date: 12-Mar-2023
    • (2023)An Effective Macro Placement Algorithm Based On Curiosity-Driven Reinforcement Learning2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218370(364-368)Online publication date: 8-May-2023
    • (2022)RTL-MPProceedings of the 2022 International Symposium on Physical Design10.1145/3505170.3506731(3-11)Online publication date: 13-Apr-2022
    • (2022)PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and RoutabilityIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.320194630:11(1783-1793)Online publication date: Nov-2022
    • (2021)Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical MethodsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.304772440:12(2542-2555)Online publication date: Dec-2021
    • (2021)Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643544(1-8)Online publication date: 1-Nov-2021
    • (2021)DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643441(1-8)Online publication date: 1-Nov-2021

    View Options

    Get Access

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media