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Formal verification of iterative algorithms in microprocessors

Authors:

Mark D. Aagaard,

Robert B. Jones,

Katherine R. Kohatsu,

Carl-Johan H. SegerAuthors Info & Claims

DAC '00: Proceedings of the 37th Annual Design Automation Conference

Pages 201 - 206

https://doi.org/10.1145/337292.337388

Published: 01 June 2000 Publication History

Abstract

Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating internal state such as the program counter; floating-point circuits perform divide and square root computations iteratively. Iterative algorithms often have complex implementations because of performance optimizations like result speculation, re-timing and circuit redundancies. Verifying these iterative circuits against high-level specifications requires two steps: reasoning about the algorithm itself and verifying the implementation against the algorithm. In this paper we discuss the verification of four iterative circuits from Intel microprocessor designs. These verifications were performed using Forte, a custom-built verification system; we discuss the Forte features necessary for our approach. Finally, we discuss how we maintained these proofs in the face of evolving design implementations.

References

[1]

M. D. Aagaard, R. B. Jones, and C.-J. H. Seger. Combining theorem proving and trajectory evaluation in an industrial environment. In DAC, pages 538-541. ACM/IEEE, July 1998.]]

Digital Library

[2]

M. D. Aagaard, R. B. Jones, and C.-J. H. Seger. Formal verification using parametric representations of Boolean constraints. In DAC, July 1999.]]

Digital Library

[3]

M. D. Aagaard, R. B. Jones, and C.-J. H. Seger. Lifted-fl: A pragmatic implementation of combined model checking and theorem proving. In L. Thery, editor, Theorem Proving in Higher Order Logics. Springer Verlag; New York, Sept. 1999.]]

Digital Library

[4]

G. Barrett. Formal methods applied to a floating-point number system. IEEE Trans. on Soft. Eng., 15(5):611-621, May 1989.]]

Digital Library

[5]

R.E. Bryant. Bit-level analysis of an SRT divider circuit. In DAC, pages 661-665, New York, June 1996. ACM.]]

Digital Library

[6]

J. R. Burch. Trace Algebra for Automatic Verification of Real-Time Concurrent Systems. PhD thesis, Comp. Sci. Dept, Carnegie Mellon Univ., 1992.]]

Digital Library

[7]

Y.-A. Chen, E. Clarke, E-H. Ho, Y. Hoskote, T. Kam, M. Khaira, J. O'Leary, and X. Zhao. Verification of all circuits in a floating-point unit using word-level model checking. In M. Srivas and A. Camilleri, editors, Formal Methods in CAD, volume 1166 of LNCS, pages 19-33, Palo Alto, CA, USA, Nov. 1996.]]

Digital Library

[8]

E. M. Clarke, S. M. German, and X. Zhao. Verifying the SRT division algorithm using theorem proving techniques. In Rajeev Alur and Thomas A. Henzinger, editors, CAV, volume 1102 of LNCS, pages 111-122, New Brunswick, NJ, USA, July 1996.]]

Digital Library

[9]

E.M. Clarke, O. Grumberg, and D. E. Long. Model checking and abstraction. ACM Trans. on Prog. Lang. and Systems, 16(5):1512-1542, Sept. 1994.]]

Digital Library

[10]

D. Gries. The Science of Programming. Springer-Verlag, 1981.]]

Digital Library

[11]

S. Hazelhurst and C.-J. H. Seger. Symbolic trajectory evaluation. In T. Kropf, editor, Formal Hardware Verification, chapter 1, pages 3-78. Springer Verlag; New York, 1997.]]

Digital Library

[12]

J.L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Inc., 1990. Second edition, 1995.]]

Digital Library

[13]

A. Kaldewaij. Programming: The Derivation of Algorithms. Prentice-Hall, 1990.]]

Digital Library

[14]

R. E Kurshan. Computer-Aided Verification of Coordinating Processes: The Automata-Theoretic Approach. Princeton Univ. Press, 1994.]]

Digital Library

[15]

J. S. Moore, T. W. Lynch, and M. Kaufmann. A mechanically checked proof of the AMD K-5 86 floating point division program. IEEE Trans. on Comp., 47(9):913-926, Sept. 1998.]]

Digital Library

[16]

J. O'Leary, X. Zhao, R. Gerth, and C.-J. H. Seger. Formally verifying IEEE compliance of floating-point hardware. Intel Technology Journal, Q 1, Feb. 1999.]]

[17]

J.W. O'Leary, M. E. Leeser, J. Y. Hickey, and M. D. Aagaard. Non-restoring integer square root: A case study in design by principled optimization. In Theorem Provers in Circuit Design. Springer Verlag; New York, Sept. 1994.]]

Digital Library

[18]

D. M. Russinoff. A mechanically checked proof of IEEE compliance of the floating point multiplication, division and square root algorithms of the AMD-K7 processor. J. of Comp. Math., 1:148-200, 1998. London Mathematical Soc.]]

[19]

C.-J. Seger. Voss i A formal hardware verification system user's guide. Technical Report 93-45, Dept. of Comp. Sci., Univ. of British Columbia, 1993.]]

Digital Library

[20]

C.-J. H. Seger and R. E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6(2):147-189, Mar. 1995.]]

Digital Library

Cited By

Goel SRay S(2022)Microprocessor Assurance and the Role of Theorem ProvingHandbook of Computer Architecture10.1007/978-981-15-6401-7_38-1(1-43)Online publication date: 12-Aug-2022
https://doi.org/10.1007/978-981-15-6401-7_38-1
Kaivola RO’Leary J(2022)Verification of Arithmetic and Datapath Circuits with Symbolic SimulationHandbook of Computer Architecture10.1007/978-981-15-6401-7_37-1(1-52)Online publication date: 2-Jun-2022
https://doi.org/10.1007/978-981-15-6401-7_37-1
Todorov VTaha SBoulanger FHernandez A(2019)Proving Properties of Discrete-Valued Functions Using Deductive Proof: Application to the Square RootModeling and Analysis of Information Systems10.18255/1818-1015-2019-4-520-53326:4(520-533)Online publication date: 27-Dec-2019
https://doi.org/10.18255/1818-1015-2019-4-520-533
Show More Cited By

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Formal verification of iterative algorithms in microprocessors

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cover image ACM Conferences

DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

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Published: 01 June 2000

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Cited By

Goel SRay S(2022)Microprocessor Assurance and the Role of Theorem ProvingHandbook of Computer Architecture10.1007/978-981-15-6401-7_38-1(1-43)Online publication date: 12-Aug-2022
https://doi.org/10.1007/978-981-15-6401-7_38-1
Kaivola RO’Leary J(2022)Verification of Arithmetic and Datapath Circuits with Symbolic SimulationHandbook of Computer Architecture10.1007/978-981-15-6401-7_37-1(1-52)Online publication date: 2-Jun-2022
https://doi.org/10.1007/978-981-15-6401-7_37-1
Todorov VTaha SBoulanger FHernandez A(2019)Proving Properties of Discrete-Valued Functions Using Deductive Proof: Application to the Square RootModeling and Analysis of Information Systems10.18255/1818-1015-2019-4-520-53326:4(520-533)Online publication date: 27-Dec-2019
https://doi.org/10.18255/1818-1015-2019-4-520-533
Haghbayan MAlizadeh BBehnam PSafari S(2014)Formal Verification and Debugging of Array Dividers with Auto-correction MechanismProceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems10.1109/VLSID.2014.21(80-85)Online publication date: 5-Jan-2014
https://dl.acm.org/doi/10.1109/VLSID.2014.21
Haghbayan MAlizadeh BRahmani ALiljeberg PTenhunen H(2014)Automated formal approach for debugging dividers using dynamic specification2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT.2014.6962068(264-269)Online publication date: Oct-2014
https://doi.org/10.1109/DFT.2014.6962068
Ecker WEsen VFindenig RSteininger TVelten M(2010)Model reduction techniques for the formal verification of hardware dependent software2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)10.1109/HLDVT.2010.5496647(148-153)Online publication date: Jun-2010
https://doi.org/10.1109/HLDVT.2010.5496647
Abed SMohamed OAl-Sammane G(2009)An abstract reachability approach by combining HOL induction and multiway decision graphsJournal of Computer Science and Technology10.1007/s11390-009-9205-824:1(76-95)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1007/s11390-009-9205-8
Flaisher AGluska ASingerman E(2007)Case study: Integrating FV and DV in the Verification of the Intel® Core^{TM} 2 Duo MicroprocessorFormal Methods in Computer Aided Design (FMCAD'07)10.1109/FAMCAD.2007.38(192-195)Online publication date: Nov-2007
https://doi.org/10.1109/FAMCAD.2007.38
Xiong HCurzon PTahar SBlandford A(2007)Providing a formal linkage between MDG and HOLFormal Methods in System Design10.1007/s10703-006-0017-y30:2(83-116)Online publication date: 1-Apr-2007
https://dl.acm.org/doi/10.1007/s10703-006-0017-y
Slobodov´ A(2006)Challenges for formal verification in industrial settingProceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology10.5555/1757571.1757573(1-22)Online publication date: 26-Aug-2006
https://dl.acm.org/doi/10.5555/1757571.1757573
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