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Critical path analysis using a dynamically bounded delay model

Author:

Soha HassounAuthors Info & Claims

DAC '00: Proceedings of the 37th Annual Design Automation Conference

Pages 260 - 265

https://doi.org/10.1145/337292.337413

Published: 01 June 2000 Publication History

Abstract

This paper focuses on static timing analysis in the presence of capacitive coupling. We propose a novel gate delay model, the dynamically bounded delay model. In contrast to the min-max or bounded delay model which assumes a fixed delay range, [d_min, d_max], for each circuit component, our new model allows for the specification of delay variations and the conditions upon which the variations will hold. Novel static timing analysis algorithms can thus dynamically bound the delays. To demonstrate the effectiveness of this model and approach, we use our model to perform critical path analysis in the presence of capacitive coupling. Our experiments show that our approach avoids pessimism when compared to PERT analysis assuming worst case capacitive coupling.

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Cited By

Alladi PTragoudas S(2017)Aging-aware critical paths for process related validation in the presence of NBTI2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918356(445-448)Online publication date: Mar-2017
https://doi.org/10.1109/ISQED.2017.7918356
Flanigan ETragoudas S(2010)Identification of delay measurable PDFs using linear dependency relationshipsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201754118:6(1011-1015)Online publication date: 1-Jun-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2017541
Alexander JAgrawal V(2009)Computing bounds on dynamic power using fast zero-delay logic simulation2009 41st Southeastern Symposium on System Theory10.1109/SSST.2009.4806832(107-112)Online publication date: Mar-2009
https://doi.org/10.1109/SSST.2009.4806832
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Published In

cover image ACM Conferences

DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

Copyright © 2000 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 2000

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Cited By

Alladi PTragoudas S(2017)Aging-aware critical paths for process related validation in the presence of NBTI2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918356(445-448)Online publication date: Mar-2017
https://doi.org/10.1109/ISQED.2017.7918356
Flanigan ETragoudas S(2010)Identification of delay measurable PDFs using linear dependency relationshipsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201754118:6(1011-1015)Online publication date: 1-Jun-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2017541
Alexander JAgrawal V(2009)Computing bounds on dynamic power using fast zero-delay logic simulation2009 41st Southeastern Symposium on System Theory10.1109/SSST.2009.4806832(107-112)Online publication date: Mar-2009
https://doi.org/10.1109/SSST.2009.4806832
Feng TPatitz ZPark N(2008)A Design Method for Ultra-High Speed for A New Wave Pipeline-based Circuit2008 IEEE Instrumentation and Measurement Technology Conference10.1109/IMTC.2008.4547279(1493-1498)Online publication date: May-2008
https://doi.org/10.1109/IMTC.2008.4547279
Lin CZhou H(2007)Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With CrosstalkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88827326:7(1222-1232)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1109/TCAD.2006.888273
Song HNepal KBahar RGrodstein J(2006)Timing analysis for full-custom circuits using symbolic DC formulationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85951025:9(1815-1830)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.859510
Hassoun SCromer CCalvillo-Gamez E(2006)Static timing analysis for level-clocked circuits in the presence of crosstalkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.81620922:9(1270-1277)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2003.816209
Kim KKang S(2006)Crosstalk noise minimization in domino logic designIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.94530520:9(1091-1100)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.945305
Lin CZhou H(2005)Trade-off between latch and flop for min-period sequential circuit designs with crosstalkProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129650(329-334)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129650
Chuan Lin Hai Zhou (2005)Trade-off between latch and flop for min-period sequential circuit designs with crosstalkICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.10.1109/ICCAD.2005.1560089(329-334)Online publication date: 2005
https://doi.org/10.1109/ICCAD.2005.1560089
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