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FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design

Authors:

Sagar Karandikar,

Borivoje Nikolić,

Krste AsanovićAuthors Info & Claims

ASPLOS '20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems

Pages 715 - 731

https://doi.org/10.1145/3373376.3378455

Published: 13 March 2020 Publication History

Abstract

Achieving high-performance when developing specialized hardware/software systems requires understanding and improving not only core compute kernels, but also intricate and elusive system-level bottlenecks. Profiling these bottlenecks requires both high-fidelity introspection and the ability to run sufficiently many cycles to execute complex software stacks, a challenging combination. In this work, we enable agile full-system performance optimization for hardware/software systems with FirePerf, a set of novel out-of-band system-level performance profiling capabilities integrated into the open-source FireSim FPGA-accelerated hardware simulation platform. Using out-of-band call stack reconstruction and automatic performance counter insertion, FirePerf enables introspecting into hardware and software at appropriate abstraction levels to rapidly identify opportunities for software optimization and hardware specialization, without disrupting end-to-end system behavior like traditional profiling tools. We demonstrate the capabilities of FirePerf with a case study that optimizes the hardware/software stack of an open-source RISC-V SoC with an Ethernet NIC to achieve 8x end-to-end improvement in achievable bandwidth for networking applications running on Linux. We also deploy a RISC-V Linux kernel optimization discovered with FirePerf on commercial RISC-V silicon, resulting in up to 1.72x improvement in network performance.

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Cited By

Langehaug TGraham S(2024)CuMONITOR: Continuous Monitoring of Microarchitecture for Software Task Identification and ClassificationDigital Threats: Research and Practice10.1145/36528615:3(1-22)Online publication date: 28-Mar-2024
https://dl.acm.org/doi/10.1145/3652861
Gottschall BEeckhout LJahre MSolihin YHeinrich M(2023)TEA: Time-Proportional Event AnalysisProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589058(1-13)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589058
Gottschall Bde Santana SJahre M(2023)Balancing Accuracy and Evaluation Overhead in Simulation Point Selection2023 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC59245.2023.00019(43-53)Online publication date: 1-Oct-2023
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cover image ACM Conferences

ASPLOS '20: Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems

March 2020

1412 pages

ISBN:9781450371025

DOI:10.1145/3373376

General Chair:
James Larus
EPFL
,
Program Chairs:
Luis Ceze
University of Washington
,
Karin Strauss
Microsoft

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https://dl.acm.org/doi/10.1145/3652861
Gottschall BEeckhout LJahre MSolihin YHeinrich M(2023)TEA: Time-Proportional Event AnalysisProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589058(1-13)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589058
Gottschall Bde Santana SJahre M(2023)Balancing Accuracy and Evaluation Overhead in Simulation Point Selection2023 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC59245.2023.00019(43-53)Online publication date: 1-Oct-2023
https://doi.org/10.1109/IISWC59245.2023.00019
Vahdatniya PSharifian AHojabr RShriraman AKloeckner AMoreira J(2022)mu-grindProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1145/3559009.3569671(346-358)Online publication date: 8-Oct-2022
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