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Gated-V_dd: a circuit technique to reduce leakage in deep-submicron cache memories

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T. N. VijaykumarAuthors Info & Claims

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

Pages 90 - 95

https://doi.org/10.1145/344166.344526

Published: 01 August 2000 Publication History

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Abstract

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across appli?cations. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruc?tion caches. We propose, gated-V_dd, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V_dd together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.

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Huq SShihab SBaroi OAura SIshtiak KBiswas S(2023)Low Leakage CMOS Design Technique with Stable State RetentionIETE Journal of Research10.1080/03772063.2023.220807670:4(4104-4113)Online publication date: 9-May-2023
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Index Terms

Gated-V_dd: a circuit technique to reduce leakage in deep-submicron cache memories
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Hardware validation

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Published In

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

August 2000

313 pages

ISBN:1581131909

DOI:10.1145/344166

Editors:
David Blaauw
Motorola, Inc., Austin, TX
,
Christian Enz
CSEM, Maladière, Switzerland
,
Thad Gabara
Lucent Technologies
,
Enrico Macii
Politenico di Torino, Turin, Italy

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Association for Computing Machinery

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Published: 01 August 2000

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ISLPED00: International Symposium on Low Power Electronic Design

July 25 - 27, 2000

Rapallo, Italy

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https://doi.org/10.1109/TC.2024.3457734
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Gated-diode FinFET DRAMs: Device and circuit design-considerations

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

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Gated-diode FinFET DRAMs: Device and circuit design-considerations

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

2 × VDD IO buffer with 1 × VDD devices considering hot-carrier and gate-oxide reliability issues

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