Cited By
View all- Joshi RZaman MKatkoori S(2022)Fast Sobel Edge Detection for IoT Edge DevicesSN Computer Science10.1007/s42979-022-01165-23:4Online publication date: 22-May-2022
Early Design Space Exploration Framework for Memristive Crossbar Arrays
Article No.: 42, Pages 1 - 26
Abstract
For memristive crossbar arrays, currently, no high-level design validation and early space exploration tools exist in the literature. Such tools are essential to quickly verify the design functionality as well as compare design alternatives in terms of power and performance. In this work, we propose a VHDL-based framework that enables us to quickly perform behavioral simulation as well as estimate dynamic energy consumption and speed of any large memristive crossbar array. We propose a high-level (VHDL) model of a memristor based on which crossbar architectures can be modeled. The individual memristor model is embedded with power and delay numbers obtained from a detailed memristor model. We demonstrate the framework for MAGIC-style memristive crossbars. We validate the framework against detailed Verilog-A based model on fifteen combinational benchmarks. For the single row model, we obtained 153x simulation speedup over HSPICE, average estimation errors of 6.64% and 0% for dynamic energy consumption and cycle-time, respectively. For the transpose model, we obtained average estimation errors of 5.51% and 10.90% for dynamic energy consumption and cycle-time, respectively. We also extend our framework to support another prominent logic style and validate through a case study. The proposed framework can be easily extended to other emerging technologies.
References
[1]
Md Adnan Zaman, Rajeev Joshi, and Srinivas Katkoori. 2020. High level modeling of memristive crossbar arrays. In 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 524–529, 2020.
[2]
William A. Wulf and Sally A. McKee. 1995. Hitting the memory wall: Implications of the obvious. ACM SIGARCH Computer Architecture News 23, 1 (1995), 20–24.
[3]
Rajeev Joshi, Md Adnan Zaman, and Srinivas Katkoori. 2020. Novel bit-sliced near-memory computing based VLSI architecture for fast Sobel edge detection in IoT edge devices. In 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS). 291–296, 2020.
[4]
Rotem Ben Hur and Shahar Kvatinsky. 2016. Memristive memory processing unit (MPU) controller for in-memory processing. In 2016 IEEE International Conference on the Science of Electrical Engineering (ICSEE). 1–5. 2016.
[5]
Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, and Uri C. Weiser. 2013. The desired memristor for circuit designers. IEEE Circuits and Systems Magazine 13, 2 (Secondquarter 2013), 17–22.
[6]
Eero Lehtonen, Jussi H. Poikonen, and Mika Laiho. 2014. Memristive stateful logic. In Memristor Networks. Springer, 603–623.
[7]
Nishil Talati, Saransh Gupta, Pravin Mane, and Shahar Kvatinsky. 2016. Logic design within memristive memories using memristor-aided loGIC (MAGIC). IEEE Transactions on Nanotechnology 15, 4 (2016), 635–650.
[8]
Ravi Nair. 2015. Evolution of memory architecture. Proc. IEEE 103, 8 (Aug 2015), 1331–1345. https://doi.org/10.1109/JPROC.2015.2435018
[9]
Rotem Ben-Hur, Ronny Ronen, Ameer Haj-Ali, Debjyoti Bhattacharjee, Adi Eliahu, Natan Peled, and Shahar Kvatinsky. 2019. SIMPLER MAGIC: Synthesis and mapping of in-memory logic executed in a single row to improve throughput. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2019), 1–1. https://doi.org/10.1109/TCAD.2019.2931188
[10]
Rahul Gharpinde, Phrangboklang Lynton Thangkhiew, Kamalika Datta, and Indranil Sengupta. 2018. A scalable in-memory logic synthesis approach using memristor crossbar. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, 2 (Feb 2018), 355–366. https://doi.org/10.1109/TVLSI.2017.2763171
[11]
Rotem Ben Hur, Nimrod Wald, Nishil Talati, and Shahar Kvatinsky. 2017. SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided logic. In 2017 IEEE/ACM International Conference on Computer-aided Design (ICCAD). 225–232. https://doi.org/10.1109/ICCAD.2017.8203782
[12]
Phrangboklang Lynton Thangkhiew, Rahul Gharpinde, and Kamalika Datta. 2018. Efficient mapping of Boolean functions to memristor crossbar using MAGIC NOR gates. IEEE Transactions on Circuits and Systems I: Regular papers 65, 8 (2018), 2466–2476.
[13]
Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 90215. ([n. d.]). http://www.eecs.berkeley.edu/alanmi/abc/.
[14]
Md Adnan Zaman, Rajeev Joshi, and Srinivas Katkoori. 2020. Analysis of radiation impact on memristive crossbar arrays. In 2020 IEEE 11th Latin American Symposium on Circuits Systems (LASCAS). 1–4.
[15]
Yuval Cassuto, Shahar Kvatinsky, and Eitan Yaakobi. 2013. Sneak-path constraints in memristor crossbar arrays. In 2013 IEEE International Symposium on Information Theory. 156–160. https://doi.org/10.1109/ISIT.2013.6620207
[16]
Md Adnan Zaman and Srinivas Katkoori. 2018. Minimizing performance and energy overheads due to fanout in memristor based logic implementations. In 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). 7–12. https://doi.org/10.1109/VLSI-SoC.2018.8644723
[17]
Md Adnan Zaman, Rajeev Joshi, and Srinivas Katkoori. 2019. Optimizing performance and energy overheads due to fanout in in-memory computing systems. In VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms. Springer International Publishing, Cham, 147–166.
[18]
Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, and Avinoam Kolodny. 2015. VTEAM: A general model for voltage-controlled memristors. IEEE Transactions on Circuits and Systems II: Express Briefs 62, 8 (Aug 2015), 786–790. https://doi.org/10.1109/TCSII.2015.2433536
[19]
Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, and Uri C. Weiser. 2013. TEAM: ThrEshold adaptive memristor model. IEEE Transactions on Circuits and Systems I: Regular Papers 60, 1 (Jan 2013), 211–221. https://doi.org/10.1109/TCSI.2012.2215714
[20]
Karel Zaplatilek. 2011. Memristor modeling in MATLAB®& Simulink®. In Proceedings of the 5th European Conference on European Computing Conference (ECC’11). World Scientific and Engineering Academy and Society (WSEAS), Stevens Point, Wisconsin, USA, 62–67. http://dl.acm.org/citation.cfm?id=1991016.1991028.
[21]
Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, and Koen Bertels. 2015. Fast Boolean logic mapped on memristor crossbar. In 2015 33rd IEEE International Conference on Computer Design (ICCD). IEEE, 335–342.
[22]
Marcello Traiola, Mario Barbareschi, and Alberto Bosio. 2018. Estimating dynamic power consumption for memristor-based CiM Architecture. Microelectronics Reliability 80 (2018), 241–248. https://doi.org/10.1016/j.microrel.2017.12.009
[23]
Rainer Waser, Regina Dittmann, Georgi Staikov, and Kristof Szot. 2009. Redox-based resistive switching memories – nanoionic mechanisms, prospects, and challenges. Advanced Materials 21, 25–26 (2009), 2632–2663. https://doi.org/10.1002/adma.200900375arXiv:https://onlinelibrary.wiley.com/doi/pdf/10.1002/adma.200900375
[24]
J. Joshua Yang, Dmitri B. Strukov, and Duncan R. Stewart. 2013. Memristive devices for computing. Nature Nanotechnology 8, 1 (01 Jan 2013), 13–24.
[25]
Leon O. Chua. 1971. Memristor-the missing circuit element. IEEE Transactions on Circuit Theory 18, 5 (September 1971), 507–519. https://doi.org/10.1109/TCT.1971.1083337
[26]
Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart, and R. Stanley Williams. 2008. The missing memristor found. Nature 453, 7191 (2008), 80–83.
[27]
Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, and Koen Bertels. 2016. Boolean logic gate exploration for memristor crossbar. In 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 1–6.
[28]
Julien Borghetti, Zhiyong Li, Joseph Straznicky, Xuema Li, Douglas A. A. Ohlberg, Wei Wu, Duncan R. Stewart, and R. Stanley Williams. 2009. A hybrid nanomemristor/transistor logic circuit capable of self-programming. Proceedings of the National Academy of Sciences 106, 6 (2009), 1699–1703.
[29]
Garrett S. Rose, Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, and Robinson E. Pino. 2011. Leveraging memristive systems in the construction of digital logic circuits. Proc. IEEE 100, 6 (2011), 2033–2049.
[30]
Julien Borghetti, Gregory S. Snider, Philip J. Kuekes, J. Joshua Yang, Duncan R. Stewart, and R. Stanley Williams. 2010. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464, 7290 (2010), 873–876.
[31]
Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, and Uri C. Weiser. 2014. MAGIC—Memristor-Aided Logic. IEEE Transactions on Circuits and Systems II: Express Briefs 61, 11 (2014), 895–899.
[32]
Yogesh N. Joglekar and Stephen J. Wolf. 2009. The elusive memristor: Properties of basic electrical circuits. European Journal of Physics 30, 4 (May 2009), 661–675. https://doi.org/10.1088/0143-0807/30/4/001
[33]
Matthew D. Picket, Dmitri B. Strukov, Julien L. Borghetti, J. Joshua Yang, Gregory S. Snider, Duncan R. Stewart, and R. Stanley Williams. 2009. Switching dynamics in titanium dioxide memristive devices. Journal of Applied Physics 106, 7 (2009), 074508. arXiv:https://doi.org/10.1063/1.3236506
[34]
Hisham Abdalla and Matthew D. Pickett. 2011. SPICE modeling of memristors. In 2011 IEEE International Symposium of Circuits and Systems (ISCAS). 1832–1835. https://doi.org/10.1109/ISCAS.2011.5937942
[35]
Zdeněk Biolek, Dalibor Biolek, and Viera Biolkova. 2009. SPICE model of memristor with nonlinear dopant drift. Radioengineering 18, 2 (June 2009), 210–214.
[36]
Zizhen Jiang, Yi Wu, Shimeng Yu, Lin Yang, Kay Song, Zia Karim, and H.-S. Philip Wong. 2016. A compact model for metal–oxide resistive random access memory with experiment verification. IEEE Transactions on Electron Devices 63, 5 (2016), 1884–1892.
[37]
Gerardo González-Cordero, Juan Bautista Roldan Aranda, Francisco Jiménez-Molinos, Jordi Suñè, Shibing Long, and Ming Liu. 2016. A new compact model for bipolar RRAMs based on truncated-cone conductive filaments—a Verilog-A approach. Semiconductor Science and Technology 31, 11 (Oct 2016), 115013. DOI:
[38]
Toufik Sadi, Adnan Mehonic, Luca Montesi, Mark Buckwell, Anthony Kenyon, and Asen Asenov. 2018. Investigation of resistance switching in SiOx RRAM cells using a 3D multi-scale kinetic Monte Carlo simulator. Journal of Physics: Condensed Matter 30, 8 (2018), 084005.
[39]
Nikhil Bansal, Kanishka Lahiri, and Anand Raghunathan. 2007. Automatic power modeling of infrastructure IP for system-on-chip power analysis. In 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID’07). 513–520.
[40]
John Reuben, Rotem Ben-Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, and Shahar Kvatinsky. 2017. Memristive logic: A framework for evaluation and comparison. In 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). 1–8.
[41]
Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, and Koen Bertels. 2018. A mapping methodology of Boolean logic circuits on memristor crossbar. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 2 (2018), 311–323.
[42]
Lei Xie. 2019. Mosaic: An automated synthesis flow for Boolean logic based on memristor crossbar. In ASP-DAC. 432–437.
[43]
Lei Xie, Hao Cai, Chao Wang, and Jun Yang. 2020. Towards an automated design flow for memristor based VLSI circuits. Integration 70 (2020), 21–31. https://doi.org/10.1016/j.vlsi.2019.09.009
[44]
Jeffry Louis, Barak Hoffer, and Shahar Kvatinsky. 2019. Performing memristor-aided logic (MAGIC) using STT-MRAM. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS). 787–790.
[45]
Predictive Technology Model (PTM) [Online]. Available: http://ptm.asu.edu/.
[46]
Fuxi Cai, Justin M. Correll, Seung Hwan Lee, Yong Lim, Vishishtha Bothra, Zhengya Zhang, Michael P. Flynn, and Wei D. Lu. 2019. A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations. Nature Electronics 2, 7 (2019), 290–299.
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Publication History
Published: 12 January 2022
Accepted: 01 April 2021
Revised: 01 January 2021
Received: 01 August 2020
Published in JETC Volume 18, Issue 2
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View all- Joshi RZaman MKatkoori S(2022)Fast Sobel Edge Detection for IoT Edge DevicesSN Computer Science10.1007/s42979-022-01165-23:4Online publication date: 22-May-2022
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