research-article

SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture

Authors:

Li JiangAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1105 - 1110

https://doi.org/10.1145/3489517.3530592

Published: 23 August 2022 Publication History

Abstract

Event-driven spiking neural networks (SNNs) have shown great promise for being strikingly energy-efficient. SNN neurons integrate the spikes, accumulate the membrane potential, and fire output spike when the potential exceeds a threshold. Existing SNN accelerators, however, have to carry out such accumulation-comparison operation in serial. Repetitive spike generation at each time step not only increases latency as well as overall energy budget, but also incurs memory access overhead of fetching membrane potentials, both of which lessen the efficiency of SNN accelerators. Meanwhile, inherent highly sparse spikes of SNNs lead to imbalanced workloads among neurons that hurdle the utilization of processing elements (PEs).

This paper proposes SATO, a temporal-parallel SNN accelerator that accumulates the membrane potential for all time steps in parallel. SATO architecture contains a novel binary adder-search tree to generate the output spike train, which decouples the chronological dependence in the accumulation-comparison operation. Moreover, SATO can evenly dispatch the compressed workloads to all PEs with maximized data locality of input spike trains based on a bucket-sort-based method. Our evaluations show that SATO outperforms the previous ANN accelerator 8-bit version of "Eyeriss" by 30.9× in terms of speedup and 12.3×, in terms of energy-saving. Compared with the state-of-the-art SNN accelerator "SpinalFlow", SATO can also achieve 6.4× performance gain and 4.8× energy reduction, which is quite impressive for inference.

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Cited By

Zhao YMa SLiu HHuang L(2024)EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNsACM Transactions on Design Automation of Electronic Systems10.1145/364313429:3(1-28)Online publication date: 14-Mar-2024
https://dl.acm.org/doi/10.1145/3643134
Jiang YLun LWang JYin MLiu HDai ZCui XCui X(2024)SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558351(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558351
Mao RTang LYuan XLiu YZhou J(2024)Stellar: Energy-Efficient and Low-Latency SNN Algorithm and Hardware Co-Design with Spatiotemporal Computation2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00023(172-185)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00023
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

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Publication History

Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Zhao YMa SLiu HHuang L(2024)EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNsACM Transactions on Design Automation of Electronic Systems10.1145/364313429:3(1-28)Online publication date: 14-Mar-2024
https://dl.acm.org/doi/10.1145/3643134
Jiang YLun LWang JYin MLiu HDai ZCui XCui X(2024)SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558351(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10558351
Mao RTang LYuan XLiu YZhou J(2024)Stellar: Energy-Efficient and Low-Latency SNN Algorithm and Hardware Co-Design with Spatiotemporal Computation2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00023(172-185)Online publication date: 2-Mar-2024
https://doi.org/10.1109/HPCA57654.2024.00023
Li JShen GZhao DZhang QZeng Y(2023)FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327934931:8(1178-1191)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3279349
Liu FWang ZZhao WChen YYang TYang XJiang L(2022)Randomize and Match: Exploiting Irregular Sparsity for Energy Efficient Processing in SNNs2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00073(451-454)Online publication date: Oct-2022
https://doi.org/10.1109/ICCD56317.2022.00073

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