research-article

Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array

Authors:

Kenli LiAuthors Info & Claims

ACM Transactions on Embedded Computing Systems, Volume 22, Issue 6

Article No.: 93, Pages 1 - 22

https://doi.org/10.1145/3549937

Published: 09 November 2023 Publication History

Abstract

Transformer model architectures have recently received great interest in natural language, machine translation, and computer vision, where attention mechanisms are their building blocks. However, the attention mechanism is expensive because of its intensive matrix computations and complicated data flow. The existing hardware architecture has some disadvantages for the computing structure of attention, such as inflexibility and low efficiency. Most of the existing papers accelerate attention by reducing the amount of computation through various pruning algorithms, which will affect the results to a certain extent with different sparsity. This paper proposes the hardware accelerator for the multi-head attention (MHA) on field-programmable gate arrays (FPGAs) with reconfigurable architecture, efficient systolic array, and hardware-friendly radix-2 softmax. We propose a novel method called Four inputs Processing Element (FPE) to double the computation rate of the data-aware systolic array (SA) and make it efficient and load balance. Especially, the computation framework is well designed to ensure the utilization of SA efficiently. Our design is evaluated on a Xilinx Alveo U250 card, and the proposed architecture achieves 51.3×, 17.3× improvement in latency, and 54.4×, 17.9× energy savings compared to CPU and GPU.

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Cited By

Wei XWang CYue HTan JGuan ZJiang NZheng XZhao JQiu M(2024)ReIPE: Recycling Idle PEs in CNN Accelerator for Vulnerable Filters Soft-Error DetectionACM Transactions on Architecture and Code Optimization10.1145/3674909Online publication date: 28-Jun-2024
https://dl.acm.org/doi/10.1145/3674909
Qin YLou WWang CGong LZhou X(2024)Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention FusionProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658810(599-603)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658810
Wu JSong MZhao JSo H(2024)A Case for Low Bitwidth Floating Point Arithmetic on FPGA for Transformer Based DNN Inference2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00045(178-185)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00045
Show More Cited By

Index Terms

Accelerating Attention Mechanism on FPGAs based on Efficient Reconfigurable Systolic Array
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Systolic arrays
  2. Embedded and cyber-physical systems
    1. System on a chip
2. Computing methodologies
  1. Artificial intelligence
    1. Natural language processing
      1. Machine translation

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 22, Issue 6

November 2023

428 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3632298

Editor:
Tulika Mitra
National University of Singapore, Singapore

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 09 November 2023

Online AM: 20 July 2022

Accepted: 10 July 2022

Revised: 19 May 2022

Received: 31 December 2021

Published in TECS Volume 22, Issue 6

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Key-Area Research and Development Program of Guangdong Province
Natural Science Foundation of Hunan Province
NSFC
Open Research Projects of Zhejiang Lab
Cultivation of Shenzhen Excellent Technological and Innovative Talents (Ph.D. Basic Research Started)
Basic research of Shenzhen Science and technology Plan

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Cited By

Wei XWang CYue HTan JGuan ZJiang NZheng XZhao JQiu M(2024)ReIPE: Recycling Idle PEs in CNN Accelerator for Vulnerable Filters Soft-Error DetectionACM Transactions on Architecture and Code Optimization10.1145/3674909Online publication date: 28-Jun-2024
https://dl.acm.org/doi/10.1145/3674909
Qin YLou WWang CGong LZhou X(2024)Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention FusionProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658810(599-603)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658810
Wu JSong MZhao JSo H(2024)A Case for Low Bitwidth Floating Point Arithmetic on FPGA for Transformer Based DNN Inference2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00045(178-185)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00045
Chen YLi TChen XCai ZSu T(2023)High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate ArraysElectronics10.3390/electronics1204082212:4(822)Online publication date: 6-Feb-2023
https://doi.org/10.3390/electronics12040822
Taka EArora AWu KMarculescu D(2023)MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine2023 International Conference on Field Programmable Technology (ICFPT)10.1109/ICFPT59805.2023.00016(96-105)Online publication date: 12-Dec-2023
https://doi.org/10.1109/ICFPT59805.2023.00016
Chen RZhang HYu JWang K(2023)FPGA Accelerating Multi-Source Transfer Learning with GAT for Bioactivities of Ligands Targeting Orphan G Protein-Coupled Receptors2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL60245.2023.00054(317-321)Online publication date: 4-Sep-2023
https://doi.org/10.1109/FPL60245.2023.00054
Wojcicki FQue ZTapper ALuk W(2022)Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments2022 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT56656.2022.9974463(1-8)Online publication date: 5-Dec-2022
https://doi.org/10.1109/ICFPT56656.2022.9974463

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