Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.1145/3566097.3568360acmconferencesArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
invited-talk

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

Published: 31 January 2023 Publication History

Abstract

The Software Defined Architectures (SODA) Synthesizer is an open-source compiler-based tool able to automatically generate domain-specialized systems targeting Application-Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) starting from high-level programming. SODA is composed of a frontend, SODA-OPT, which leverages the multilevel intermediate representation (MLIR) framework to interface with productive programming tools (e.g., machine learning frameworks), identify kernels suitable for acceleration, and perform high-level optimizations, and of a state-of-the-art high-level synthesis backend, Bambu from the PandA framework, to generate custom accelerators. One specific application of the SODA Synthesizer is the generation of accelerators to enable ultra-low latency inference and control on autonomous systems for scientific discovery (e.g., electron microscopes, sensors in particle accelerators, etc.). This paper provides an overview of the flow in the context of the generation of accelerators for edge processing to be integrated in transmission electron microscopy (TEM) devices, focusing on use cases from precision material synthesis. We show the tool in action with an example of design space exploration for inference on reconfigurable devices with a conventional deep neural network model (LeNet). Finally, we discuss the research directions and opportunities enabled by SODA in the area of autonomous control for scientific experimental workflows.

References

[1]
E. Bethel and eds. 2016. Report of the DOE Workshop on Management, Analysis, and Visualization of Experimental and Observational data - The Convergence of Data and Computing. Technical Report.
[2]
Nicolas Bohm Agostini, Serena Curzel, Vinay Amatya, Cheng Tan, Marco Minutoli, Vito Giovanni Castellana, Joseph Manzano, David Kaeli, and Antonino Tumeo. 2022. An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration. In 41st IEEE/ACM International Conference on Computer-Aided Design (ICCAD'22). To appear.
[3]
Nicolas Bohm Agostini, Serena Curzel, Jeff Zhang, Ankur Limaye, Cheng Tan, Vinay Amatya, Marco Minutoli, Vito Giovanni Castellana, Joseph Manzano, David Brooks, Gu-Yeon Wei, and Antonino Tumeo. 2022. Bridging Python to Silicon: The SODA Toolchain. IEEE Micro (2022).
[4]
Vito Giovanni Castellana and Fabrizio Ferrandi. 2013. An automated flow for the High Level Synthesis of coarse grained parallel applications. In 2013 International Conference on Field-Programmable Technology (FPT). 294--301.
[5]
Vito Giovanni Castellana, Antonino Tumeo, and Fabrizio Ferrandi. 2021. High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers. In IEEE International Parallel and Distributed Processing Symposium (IPDPS'21). 192--202.
[6]
S. Curzel, N. Bohm Agostini, S. Song, I. Dagli, A. Limaye, M. Minutoli, V. G. Castellana, V. Amatya, J. Manzano, A. Das, F. Ferrandi, and A. Tumeo. 2021. Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators. In ICCAD: International Conference On Computer Aided Design. 1--7.
[7]
J. Duarte, S. Han, P. Harris, S. Jindariani, E. Kreinar, B. Kreis, J. Ngadiuba, M. Pierini, R. Rivera, N. Tran, and Z. Wu. 2018. Fast inference of deep neural networks in FPGAs for particle physics. Journal of Instrumentation 13, 07 (jul 2018), P07027--P07027.
[8]
Fabrizio Ferrandi, Vito Giovanni Castellana, Serena Curzel, Pietro Fezzardi, Michele Fiorito, Marco Lattuada, Marco Minutoli, Christian Pilato, and Antonino Tumeo. 2021. Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications. In 58th ACM/IEEE Design Automation Conference (DAC'21). 1327--1330.
[9]
Andrew B. Kahng and Tom Spyrou. 2021. The OpenROAD Project: Unleashing Hardware Innovation. In Government Microcircuit Applications and Critical Technology Conference. 1--6.
[10]
Emir Kocer, Tsz Wai Ko, and Jörg Behler. 2021. Neural Network Potentials: A Concise Overview of Methods.
[11]
Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, and Oleksandr Zinenko. 2021. MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. In IEEE/ACM International Symposium on Code Generation and Optimization (CGO'21). 2--14.
[12]
Y. Lecun, L. Bottou, Y. Bengio, and P. Haffner. 1998. Gradient-based learning applied to document recognition. Proc. IEEE 86, 11 (1998), 2278--2324.
[13]
Haotong Liang, Valentin Stanev, Aaron Gilad Kusne, Yuto Tsukahara, Kaito Ito, Ryota Takahashi, Mikk Lippmaa, and Ichiro Takeuchi. 2022. Application of machine learning to reflection high-energy electron diffraction images for automated structural phase mapping. Phys. Rev. Materials 6 (Jun 2022), 063805. Issue 6.
[14]
John E. Mahan, Kent M. Geib, G. Y. Robinson, and Robert G. Long. 1990. A review of the geometrical fundamentals of reflection high-energy electron diffraction with application to silicon surfaces. Journal of Vacuum Science & Technology A 8, 5 (1990), 3692--3700.
[15]
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, and Luca P. Carloni. 2020. Agile SoC Development with Open ESP. In IEEE/ACM International Conference On Computer Aided Design (ICCAD'20). 1--9.
[16]
Marco Minutoli, Vito Giovanni Castellana, Nicola Saporetti, Stefano Devecchi, Marco Lattuada, Pietro Fezzardi, Antonino Tumeo, and Fabrizio Ferrandi. 2022. Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics. IEEE Trans. Comput. 71, 3 (March 2022), 520--533.
[17]
Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, and Fabrizio Ferrandi. 2015. Inter-procedural resource sharing in High Level Synthesis through function proxies. In 25th International Conference on Field Programmable Logic and Applications (FPL'15). 1--8.
[18]
Cassandra Pate, James Hart, and Mitra Taheri. 2021. RapidEELS: machine learning for denoising and classification in rapid acquisition electron energy loss spectroscopy. Scientific Reports 11 (09 2021).
[19]
Sydney R. Provence, Suresh Thapa, Rajendra Paudel, Tristan K. Truttmann, Abhinav Prakash, Bharat Jalan, and Ryan B. Comes. 2020. Machine learning analysis of perovskite oxides grown by molecular beam epitaxy. Physical Review Materials 4, 8 (aug 2020).
[20]
W. Snyder. 2022. RapidEELS. https://github.com/patecm/rapidEELS Online, accessed 11-2022.
[21]
Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Baudouin Chauviere, and Pierre-Emmanuel Gaillardon. 2019. OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. In 29th International Conference on Field Programmable Logic and Applications (FPL'19). 367--374.
[22]
Rama K. Vasudevan, Alexander Tselev, Arthur P. Baddorf, and Sergei V. Kalinin. 2014. Big-Data Reflection High Energy Electron Diffraction Analysis for Understanding Epitaxial Film Growth Processes. ACS Nano 8, 10 (2014), 10899--10908.
[23]
Ruizhe Zhao, Jianyi Cheng, Wayne Luk, and George A. Constantinides. 2022. POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. In 32nd International Conference on Field Programmable Logic and Applications (FPL'22). To appear.

Cited By

View all
  • (2024)Real-time tracking of structural evolution in 2D MXenes using theory-enhanced machine learningScientific Reports10.1038/s41598-024-66902-414:1Online publication date: 2-Aug-2024

Index Terms

  1. Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference
    January 2023
    807 pages
    ISBN:9781450397834
    DOI:10.1145/3566097
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

    Sponsors

    In-Cooperation

    • IPSJ
    • IEEE CAS
    • IEEE CEDA
    • IEICE

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 31 January 2023

    Check for updates

    Author Tags

    1. design automation
    2. edge computing
    3. high level synthesis
    4. machine learning
    5. neural networks

    Qualifiers

    • Invited-talk

    Conference

    ASPDAC '23
    Sponsor:

    Acceptance Rates

    ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;
    Overall Acceptance Rate 466 of 1,454 submissions, 32%

    Upcoming Conference

    ASPDAC '25

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)38
    • Downloads (Last 6 weeks)1
    Reflects downloads up to 09 Nov 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2024)Real-time tracking of structural evolution in 2D MXenes using theory-enhanced machine learningScientific Reports10.1038/s41598-024-66902-414:1Online publication date: 2-Aug-2024

    View Options

    Get Access

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media