Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool

Conventional standard cell libraries are composed of cells of diverse logic functions, all of which commonly and strictly maintain an equal height i.e., single-row-height. However, as the process technology node advances, large cells such as flip-flops are designed with multi-row-height to balance the horizontal and vertical pin accessibility to the cells. For designs with cell instances of mixed-height i.e., single-row-height and multi-row-height cell instances, the placement legalization problem becomes more difficult since the additional power-rail alignment constraint should be imposed to the multi-row-height cells. In this work, we propose a polynomial-time refinement algorithm amenable to the placement legalization of mixed-height cells. Precisely, from a placement legalization delivered by a state-of-the-art commercial tool, our algorithm iteratively and effectively refines the legalization by employing our comprehensive cell swapping mechanism with efficient internal data structures for cost computation. Through experiments with ISPD2015 benchmark circuits, it is shown that our method is able to simultaneously reduce the total displacement and HPWL by 16.7% and 20.8% on average over the legalization results produced by the state-of-the-art commercial tool for designs with the chip utilization over 0.8, respectively.