research-article

LUT-based RRAM Model for Neural Accelerator Circuit Simulation

Authors:

Emilio Pérez-Bosch Quesada,

Bakr Al Beattie,

Karlheinz Ochs,

Eduardo Pérez,

Philip Ostrovskyy,

Christian Wenger,

Gerhard KahmenAuthors Info & Claims

NANOARCH '23: Proceedings of the 18th ACM International Symposium on Nanoscale Architectures

Article No.: 35, Pages 1 - 6

https://doi.org/10.1145/3611315.3633273

Published: 25 January 2024 Publication History

Abstract

Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.

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Cited By

Wen JVargas FZhu FReiser DBaroni AFritscher MPerez EReichenbach MWenger CKrstic M(2024)Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment2024 IEEE 25th Latin American Test Symposium (LATS)10.1109/LATS62223.2024.10534601(1-6)Online publication date: 9-Apr-2024
https://doi.org/10.1109/LATS62223.2024.10534601

Index Terms

LUT-based RRAM Model for Neural Accelerator Circuit Simulation
1. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging tools and methodologies
    2. Memory and dense storage

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cover image ACM Other conferences

NANOARCH '23: Proceedings of the 18th ACM International Symposium on Nanoscale Architectures

December 2023

222 pages

ISBN:9798400703256

DOI:10.1145/3611315

Copyright © 2023 ACM.

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Publication History

Published: 25 January 2024

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Deutsche Forschungsgemeinschaft (DFG)

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NANOARCH '23

NANOARCH '23: 18th ACM International Symposium on Nanoscale Architectures

December 18 - 20, 2023

Dresden, Germany

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Cited By

Wen JVargas FZhu FReiser DBaroni AFritscher MPerez EReichenbach MWenger CKrstic M(2024)Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment2024 IEEE 25th Latin American Test Symposium (LATS)10.1109/LATS62223.2024.10534601(1-6)Online publication date: 9-Apr-2024
https://doi.org/10.1109/LATS62223.2024.10534601

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