research-article

Fast, Robust and Transferable Prediction for Hardware Logic Synthesis

Authors:

Lisa Wu WillsAuthors Info & Claims

MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture

Pages 167 - 179

https://doi.org/10.1145/3613424.3623794

Published: 08 December 2023 Publication History

Abstract

The increasing complexity of computer chips and the slow logic synthesis process have become major bottlenecks in the hardware design process, also hindering the ability of hardware generators to make informed design decisions while considering hardware costs. While various models have been proposed to predict physical characteristics of hardware designs, they often suffer from limited domain adaptability and open-source hardware design data scarcity.

In this paper, we present SNS v2, a fast, robust, and transferable hardware synthesis predictor based on deep learning models. Inspired by modern natural language processing models, SNS v2 adopts a three-phase training approach encompassing pre-training, fine-tuning, and domain adaptation, enabling it to leverage more abundant unlabeled and off-domain training data. Additionally, we propose a novel contrastive learning approach based on circuit equivalence to enhance model robustness. Our experiments demonstrate that SNS v2 achieves two to three orders of magnitude faster speed compared to conventional EDA tools, while maintaining state-of-the-art prediction accuracy. We also show that SNS v2 can be seamlessly integrated into hardware generator frameworks for real-time cost estimation, resulting in higher quality design recommendations in a significantly reduced time frame.

References

[1]

Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanović, and Borivoje Nikolić. 2020. Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. IEEE Micro 40, 4 (2020), 10–21. https://doi.org/10.1109/MM.2020.2996616

Digital Library

[2]

Krste Asanovic, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, 2016. The rocket chip generator. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17 4 (2016).

Digital Library

[3]

Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup Lee, Andrew Waterman, Rimas Avižienis, John Wawrzynek, and Krste Asanović. 2012. Chisel: Constructing Hardware in a Scala Embedded Language. In Proceedings of the 49th Annual Design Automation Conference (San Francisco, California) (DAC ’12). Association for Computing Machinery, New York, NY, USA, 1216–1225. https://doi.org/10.1145/2228360.2228584

Digital Library

[4]

Xiangning Chen, Chen Liang, Da Huang, Esteban Real, Kaiyuan Wang, Yao Liu, Hieu Pham, Xuanyi Dong, Thang Luong, Cho-Jui Hsieh, Yifeng Lu, and Quoc V. Le. 2023. Symbolic Discovery of Optimization Algorithms. https://arxiv.org/abs/2302.06675

[5]

Jacob Devlin, Ming-Wei Chang, Kenton Lee, and Kristina Toutanova. 2019. BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding. In Proceedings of the 2019 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, Volume 1 Long and Short Papers. Association for Computational Linguistics, Minneapolis, Minnesota, USA, 4171–4186. https://doi.org/10.18653/v1/N19-1423

[6]

Thomas Elsken, Jan Hendrik Metzen, and Frank Hutter. 2019. Neural architecture search: A survey. The Journal of Machine Learning Research 20, 1 (2019), 1997–2017.

Digital Library

[7]

Hasan Genc, Seah Kim, Alon Amid, Ameer Haj-Ali, Vighnesh Iyer, Pranav Prakash, Jerry Zhao, Daniel Grubb, Harrison Liew, Howard Mao, Albert Ou, Colin Schmidt, Samuel Steffl, John Wright, Ion Stoica, Jonathan Ragan-Kelley, Krste Asanovic, Borivoje Nikolic, and Yakun Sophia Shao. 2021. Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration. In 2021 58th ACM/IEEE Design Automation Conference (DAC). 769–774. https://doi.org/10.1109/DAC18074.2021.9586216

Digital Library

[8]

R. Goldman, K. Bartleson, T. Wood, K. Kranen, C. Cao, V. Melikyan, and G. Markosyan. 2009. Synopsys’ open educational design kit: Capabilities, deployment and future. In 2009 IEEE International Conference on Microelectronic Systems Education. 20–24. https://doi.org/10.1109/MSE.2009.5270840

[9]

Aditya Grover and Jure Leskovec. 2016. node2vec: Scalable Feature Learning for Networks. In Proceedings of the 22nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining. Association for Computing Machinery, San Francisco, California, USA, 4171–4186. https://doi.org/10.1145/2939672.2939754

Digital Library

[10]

Mai Lan Ha and Volker Blanz. 2021. Deep ranking with adaptive margin triplet loss. arXiv preprint arXiv:2107.06187 (2021).

[11]

Kaiming He, Xiangyu Zhang, Shaoqing Ren, and Jian Sun. 2016. Deep Residual Learning for Image Recognition. In 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR). Las Vegas, NV, USA, 770–778. https://doi.org/10.1109/CVPR.2016.90

[12]

Adam Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, and Jonathan Bachrach. 2017. Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 209–216. https://doi.org/10.1109/ICCAD.2017.8203780

Digital Library

[13]

Diederik P. Kingma and Jimmy Ba. 2017. Adam: A Method for Stochastic Optimization. arxiv:1412.6980 [cs.LG]

[14]

Thomas N. Kipf and Max Welling. 2016. Semi-Supervised Classification with Graph Convolutional Networks. CoRR abs/1609.02907 (2016). arXiv:1609.02907http://arxiv.org/abs/1609.02907

[15]

Yunyong Ko, Kibong Choi, Hyunseung Jei, Dongwon Lee, and Sang-Wook Kim. 2021. ALADDIN: Asymmetric Centralized Training for Distributed Deep Learning. In Proceedings of the 30th ACM International Conference on Information & Knowledge Management. Association for Computing Machinery, Virtual Event Queensland Australia, 863–872. https://doi.org/10.1145/3459637.3482412

Digital Library

[16]

Alex Krizhevsky, Vinod Nair, and Geoffrey Hinton. [n. d.]. CIFAR-10 (Canadian Institute for Advanced Research). ([n. d.]). http://www.cs.toronto.edu/ kriz/cifar.html

[17]

Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, and Tushar Krishna. 2019. Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (Columbus, OH, USA) (MICRO ’52). Association for Computing Machinery, New York, NY, USA, 754–768. https://doi.org/10.1145/3352460.3358252

Digital Library

[18]

Yi-Chen Lu, Siddhartha Nath, Sai Pentapati, and Sung Kyu Lim. 2022. ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation. ACM Trans. Des. Autom. Electron. Syst. (oct 2022). https://doi.org/10.1145/3569942 Just Accepted.

Digital Library

[19]

Tomas Mikolov, Ilya Sutskever, Kai Chen, Greg Corrado, and Jeffrey Dean. 2013. Distributed Representations of Words and Phrases and Their Compositionality. In Proceedings of the 26th International Conference on Neural Information Processing Systems - Volume 2 (Lake Tahoe, Nevada) (NIPS’13). Curran Associates Inc., Red Hook, NY, USA, 3111–3119.

Digital Library

[20]

Thierry Moreau, Tianqi Chen, Luis Vega, Jared Roesch, Eddie Yan, Lianmin Zheng, Josh Fromm, Ziheng Jiang, Luis Ceze, Carlos Guestrin, and Arvind Krishnamurthy. 2019. A Hardware–Software Blueprint for Flexible Deep Learning Specialization. IEEE Micro 39, 5 (2019), 8–16. https://doi.org/10.1109/MM.2019.2928962

[21]

OpenAI. 2023. GPT-4 Technical Report. arxiv:2303.08774 [cs.CL] https://arxiv.org/abs/2303.08774

[22]

Aditya Ramesh, Prafulla Dhariwal, Alex Nichol, Casey Chu, and Mark Chen. 2022. Hierarchical Text-Conditional Image Generation with CLIP Latents. arxiv:2204.06125 [cs.CV] https://arxiv.org/abs/2210.10606

[23]

Brandon Reagen, Robert Adolf, Yakun Sophia Shao, Gu-Yeon Wei, and David Brooks. 2014. MachSuite: Benchmarks for accelerator design and customized architectures. In 2014 IEEE International Symposium on Workload Characterization (IISWC). 110–119. https://doi.org/10.1109/IISWC.2014.6983050

[24]

Colin Schmidt, Alber Ou, and Krste Asanović. 2018. Hwacha v4: Decoupled data parallel custom extension. In Proc. Inaugural RISC-V Summit. 1–40.

[25]

Juri Schmidt and Ulrich Bruning. 2015. openHMC-a configurable open-source hybrid memory cube controller. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 1–6.

[26]

Inc. Synopsys. [n. d.]. DC Ultra: Concurrent Timing, Area, Power and Test Optimization. Synopsys, Inc.https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra.html

[27]

Christian Szegedy, Wei Liu, Yangqing Jia, Pierre Sermanet, Scott Reed, Dragomir Anguelov, Dumitru Erhan, Vincent Vanhoucke, and Andrew Rabinovich. 2015. Going deeper with convolutions. In 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR). Boston, MA, USA, 1–9. https://doi.org/10.1109/CVPR.2015.7298594

[28]

Hugo Touvron, Thibaut Lavril, Gautier Izacard, Xavier Martinet, Marie-Anne Lachaux, Timothée Lacroix, Baptiste Rozière, Naman Goyal, Eric Hambro, Faisal Azhar, Aurelien Rodriguez, Armand Joulin, Edouard Grave, and Guillaume Lample. 2023. LLaMA: Open and Efficient Foundation Language Models. arxiv:2302.13971 [cs.CL] https://arxiv.org/abs/2302.13971

[29]

Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, and Zhiru Zhang. 2020. Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. In Proceedings of the 39th International Conference on Computer-Aided Design (Virtual Event, USA) (ICCAD ’20). Association for Computing Machinery, New York, NY, USA, Article 87, 9 pages. https://doi.org/10.1145/3400302.3415657

Digital Library

[30]

Kaifan Wang, Yinan Xu, Zihao Yu, Dan Tang, Guokai Chen, Xi Chen, Lingrui Gou, Xuan Hu, Yue Jin, Qianruo Li, Xin Li, Jiawei Lin, Tong Liu, Zhigang Liu, Huaqiang Wang, Huizhe Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Ziyue Zhang, Yangyang Zhao, Yaoyang Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Wei He, Ninghui Sun, and Yungang Bao. 2023. XiangShan Open-Source High Performance RISC-V Processor Design and Implementation. Journal of Computer Research and Development 60, 3 (2023), 476–493. https://doi.org/10.7544/issn1000-1239.202221036

[31]

Minjie Wang, Da Zheng, Zihao Ye, Quan Gan, Mufei Li, Xiang Song, Jinjing Zhou, Chao Ma, Lingfan Yu, Yu Gai, Tianjun Xiao, Tong He, George Karypis, Jinyang Li, and Zheng Zhang. 2020. Deep Graph Library: A Graph-Centric, Highly-Performant Package for Graph Neural Networks. arxiv:1909.01315 [cs.LG]

[32]

Clifford Wolf, Johann Glaser, and Johannes Kepler. 2013. Yosys-A Free Verilog Synthesis Suite.

[33]

Nan Wu, Hang Yang, Yuan Xie, Pan Li, and Cong Hao. 2022. High-Level Synthesis Performance Prediction Using GNNs: Benchmarking, Modeling, and Advancing. In Proceedings of the 59th ACM/IEEE Design Automation Conference (San Francisco, California) (DAC ’22). Association for Computing Machinery, New York, NY, USA, 49–54. https://doi.org/10.1145/3489517.3530408

Digital Library

[34]

Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, and Jiang Hu. 2018. RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1–8. https://doi.org/10.1145/3240765.3240843

Digital Library

[35]

Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Chen-Chia Chang, Jingyu Pan, and Yiran Chen. 2022. Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41, 11 (2022), 4667–4680. https://doi.org/10.1109/TCAD.2022.3149977

Digital Library

[36]

Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Herbert, Jiang Hu, Yiran Chen, and Shidhartha Das. 2021. APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. In Proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture. Association for Computing Machinery, New York, NY, USA, 1–14. https://doi.org/10.1145/3466752.3480064

Digital Library

[37]

Ceyu Xu, Chris Kjellqvist, and Lisa Wu Wills. 2022. SNS’s Not a Synthesizer: A Deep-Learning-Based Synthesis Predictor. In Proceedings of the 49th Annual International Symposium on Computer Architecture (New York, New York) (ISCA ’22). Association for Computing Machinery, New York, NY, USA, 847–859. https://doi.org/10.1145/3470496.3527444

Digital Library

[38]

Yinan Xu, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, Jiawei Lin, Tong Liu, Zhigang Liu, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Yangyang Zhao, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Zihao Chen, Wei He, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, and Yungang Bao. 2022. Towards Developing High Performance RISC-V Processors Using Agile Methodology. In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). 1178–1199. https://doi.org/10.1109/MICRO56248.2022.00080

Digital Library

[39]

Chris Ying, Aaron Klein, Eric Christiansen, Esteban Real, Kevin Murphy, and Frank Hutter. 2019. NAS-Bench-101: Towards Reproducible Neural Architecture Search. In Proceedings of the 36th International Conference on Machine Learning(Proceedings of Machine Learning Research, Vol. 97), Kamalika Chaudhuri and Ruslan Salakhutdinov (Eds.). PMLR, 7105–7114. https://proceedings.mlr.press/v97/ying19a.html

[40]

Yanqing Zhang, Haoxing Ren, and Brucek Khailany. 2020. GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. In 2020 57th ACM/IEEE Design Automation Conference (DAC). 1–6. https://doi.org/10.1109/DAC18072.2020.9218643

[41]

Jerry Zhao, Animesh Agrawal, Borivoje Nikolic, and Krste Asanović. 2022. Constellation: An Open-Source SoC-Capable NoC Generator. In 2022 15th IEEE/ACM International Workshop on Network on Chip Architectures (NoCArc). 1–7. https://doi.org/10.1109/NoCArc57472.2022.9911299

[42]

Jerry Zhao, Ben Korpan, Abraham Gonzalez, and Krste Asanovic. 2020. Sonicboom: The 3rd generation berkeley out-of-order machine. In Fourth Workshop on Computer Architecture Research with RISC-V, Vol. 5.

Cited By

Chen LChen YChu ZFang WHo THuang RHuang YKhan SLi MLi XLi YLiang YLiu JLiu YLin YLuo GPan HShi ZSun GTsaras DWang RWang ZWei XXie ZXu QXue CYan JYang JYu BYuan MYoung EZeng XZhang HZhang ZZhao YZhen HZheng ZZhu BZhu KZou S(2024)Large circuit models: opportunities and challengesScience China Information Sciences10.1007/s11432-024-4155-767:10Online publication date: 25-Sep-2024
https://doi.org/10.1007/s11432-024-4155-7

Index Terms

Fast, Robust and Transferable Prediction for Hardware Logic Synthesis
1. Computing methodologies
  1. Machine learning
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
  2. Integrated circuits

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cover image ACM Conferences

MICRO '23: Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture

October 2023

1528 pages

ISBN:9798400703294

DOI:10.1145/3613424

Copyright © 2023 ACM.

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Published: 08 December 2023

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MICRO '23: 56th Annual IEEE/ACM International Symposium on Microarchitecture

October 28 - November 1, 2023

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Chen LChen YChu ZFang WHo THuang RHuang YKhan SLi MLi XLi YLiang YLiu JLiu YLin YLuo GPan HShi ZSun GTsaras DWang RWang ZWei XXie ZXu QXue CYan JYang JYu BYuan MYoung EZeng XZhang HZhang ZZhao YZhen HZheng ZZhu BZhu KZou S(2024)Large circuit models: opportunities and challengesScience China Information Sciences10.1007/s11432-024-4155-767:10Online publication date: 25-Sep-2024
https://doi.org/10.1007/s11432-024-4155-7

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