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High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing

Authors:

Cong HaoAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 49 - 54

https://doi.org/10.1145/3489517.3530408

Published: 23 August 2022 Publication History

Abstract

Agile hardware development requires fast and accurate circuit quality evaluation from early design stages. Existing work of high-level synthesis (HLS) performance prediction usually requires extensive feature engineering after the synthesis process. To expedite circuit evaluation from as early design stage as possible, we propose rapid and accurate performance prediction methods, which exploit the representation power of graph neural networks (GNNs) by representing C/C++ programs as graphs. The contribution of this work is three-fold. (1) Benchmarking. We build a standard benchmark suite with 40k C programs, which includes synthetic programs and three sets of real-world HLS benchmarks. Each program is synthesized and implemented on FPGA to obtain post place-and-route performance metrics as the ground truth. (2) Modeling. We formally formulate the HLS performance prediction problem on graphs and propose multiple modeling strategies with GNNs that leverage different trade-offs between prediction timeliness (early/late prediction) and accuracy. (3) Advancing. We further propose a novel hierarchical GNN that does not sacrifice timeliness but largely improves prediction accuracy, significantly outperforming HLS tools. We apply extensive evaluations for both synthetic and unseen real-case programs; our proposed predictor largely outperforms HLS by up to 40X and excels existing predictors by 2X to 5X in terms of resource usage and timing prediction. The benchmark and explored GNN models are publicly available at https://github.com/lydiawunan/HLS-Perf-Prediction-with-GNNs.

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Cited By

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https://doi.org/10.1109/TCAD.2024.3420904
Gao MZhao JLin ZGuo M(2024)Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546555(1-6)Online publication date: 25-Mar-2024
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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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https://doi.org/10.1109/TCAD.2024.3420904
Gao MZhao JLin ZGuo M(2024)Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546555(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546555
Qin ZBai YSohrabizadeh ADing ZHu ZSun YCong JAmrouch HHu JGarg SLin Y(2024)Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level SynthesisProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685952(1-12)Online publication date: 9-Sep-2024
https://dl.acm.org/doi/10.1145/3670474.3685952
Bai YSohrabizadeh ADing ZLiang RLi WWang DRen HSun YCong JAmrouch HHu JGarg SLin Y(2024)Learning to Compare Hardware Designs for High-Level SynthesisProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685940(1-7)Online publication date: 9-Sep-2024
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Du LLiang TZhou XGe JLi SSinha SZhao JXie ZZhang W(2024)FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/365345817:3(1-33)Online publication date: 20-Mar-2024
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Lin YDeng GPrasanna V(2024)A Unified CPU-GPU Protocol for GNN TrainingProceedings of the 21st ACM International Conference on Computing Frontiers10.1145/3649153.3649191(155-163)Online publication date: 7-May-2024
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Sohrabizadeh ABai YSun YCong J(2024)Harnessing GNNs for Robust Representation Learning in High-Level SynthesisIEEE Transactions on Circuits and Systems for Artificial Intelligence10.1109/TCASAI.2024.34855221:2(114-127)Online publication date: Dec-2024
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Bai YSohrabizadeh ADing ZLiang RLi WWang DRen HSun YCong J(2024)Learning to Compare Hardware Designs for High-Level Synthesis2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740257(1-7)Online publication date: 9-Sep-2024
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Wong SWan GLiu DWang X(2024)VGV: Verilog Generation using Visual Capabilities of Multi-Modal Large Language Models2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691753(1-5)Online publication date: 28-Jun-2024
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Levy AWalston JSamanta SRaina PDiamantidis S(2024)FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528750(1-8)Online publication date: 3-Apr-2024
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