Introduction to the Special Issue on Next-Generation On-Chip and Off-Chip Communication Architectures for Edge, Cloud and HPC

Communication is becoming increasingly important with the advent of diverse computing platforms, such as many-core CPUs, GPUs, FPGAs, machine learning (ML) accelerators, and other domain-specific processors. Movement of data is becoming a greater challenge not only within a chip but also chip-to-chip and can greatly impact overall system performance. Emerging technologies also offer a new opportunity to accelerate communication and rethink the design of interconnection networks. These trends in architecture, application, and technology require innovative communication designs, interconnection networks for on-chip networks and off-chip networks for the next generation of computing systems.

This Special Issue was created to showcase innovative research in the domain of communication architectures for Edge, Cloud and/or HPC systems. The process involved inviting submissions that were initially accepted at the IEEE/ACM Symposium on Networks-on-Chip (NOCS) 2021 to submit extended manuscripts to the Special Issue. Furthermore, the call for papers was also open to anyone who wished to submit to the Special Issue. All submitted papers went through a multi-round single-blind review process adhering to the standards of ACM JETC.

We are pleased to introduce the following paper in the Special Issue, titled “STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators,”. The focus of this paper is on optimizing the communication fabric within Deep Neural Network (DNN) accelerators – which are becoming pervasive to meet both the computational and energy-efficiency demands of modern AI/ML workloads. The paper presents a network topology optimized for performing efficient reductions within DNN accelerators. Reductions are a key computational step within DNNs and occur when performing tensor operations such as convolutions, matrix multiplications or vector dot-products. The size of the reduction depends upon the size and shape of the different layers of the DNN. However, many DNN accelerators today provide hardware support for fixed size reductions. This can lead to inefficiencies when the size of the reduction required is smaller or larger than this fixed size – especially given high diversity between layers of a DNN. This paper proposes a novel tree-based topology with additional microarchitectural features to enable reductions of arbitrary sized tensors across both space and time, enhancing the overall performance of DNN accelerators.