Revisiting Learned Index with Byte-addressable Persistent Storage
Authors: 
Rui Zhang, Yukai Huang, Sicheng Liang, Shangyi Sun, Shaonan Ma, Chengying Huan, Lulu Chen, Zhihui Lu, Yang Xu, Ming Yan, Jie WuAuthors Info & Claims
Rui Zhang, Yukai Huang, Sicheng Liang, Shangyi Sun, Shaonan Ma, Chengying Huan, Lulu Chen, Zhihui Lu, Yang Xu, Ming Yan, Jie WuAuthors Info & ClaimsPages 929 - 938
Abstract
Byte-addressable Persistent Storage (BPS), such as persistent memory and CXL-enabled SSDs, has become an extension of main memory. This opens up new possibilities for indexes that operate and persist data directly on the memory bus. Recent learned indexes exploit data distribution and have shown great potential for some workloads. Despite some work proposed for integrating learned indexes into BPS, they are mainly based on Intel’s first-generation persistent memory. The current design suffers from the following problems: 1) Excessive storage line accesses due to large node in learned indexes; 2) Inefficient concurrency control due to volatile cache; 3) Write amplification due to mismatch access granularity.
To resolve these challenges, we introduce a new learned index named PFLX, featuring three key design improvements: 1) a Storage Line-Friendly Node Layout that enhances search and insertion operations and minimizes storage line accesses through strategic use of pointers; 2) a Persistent Cache-based Lock-free Concurrency Mechanism that utilizes atomic primitives to serialize operations in leaf nodes effectively; 3) a Selective Data Flush Mechanism designed to reduce write amplification. Evaluations show that PFLX outperforms the state-of-the-art persistent indexes by 1.2 ∼ 3 ×.
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August 2024
1279 pages
ISBN:9798400717932
DOI:10.1145/3673038
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Published: 12 August 2024
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ICPP '24: the 53rd International Conference on Parallel Processing
August 12 - 15, 2024
Gotland, Sweden
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