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Generating efficient tests for continuous scan

Authors:

Sying-Jyan Wang,

Sheng-Nan ChiouAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 162 - 165

https://doi.org/10.1145/378239.378393

Published: 22 June 2001 Publication History

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Abstract

Conventional scan-based designs spend a lot of testing time in shifting test patterns and output responses, which greatly increases the testing cost. In this paper, we propose a modified approach for scan-based design in which a test is conducted in every clock cycle. This approach may significantly reduce the test application time when appropriate test vectors are applied. We develop algorithms to generate efficient test input for the test environment, and experimental results show that we can achieve high fault coverage with only about 10%-30% of the clock cycles required in conventional scan-based design.

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Cited By

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Chen JYang CLee K(2019)Test pattern generation and clock disabling for simultaneous test time and power reductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.80789022:3(363-370)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2002.807890
Jin HWang YChen NWang SZeng L(2009)Predication of Program Behaviours for Functionality TestingProceedings of the 2009 First IEEE International Conference on Information Science and Engineering10.1109/ICISE.2009.843(4993-4996)Online publication date: 26-Dec-2009
https://dl.acm.org/doi/10.1109/ICISE.2009.843
Tehranipoor MAhmed N(2008)Testing SoC Interconnects for Signal IntegrityNanometer Technology Designs High-Quality Delay Tests10.1007/978-0-387-75728-5_12(241-275)Online publication date: 2008
https://doi.org/10.1007/978-0-387-75728-5_12
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Index Terms

Generating efficient tests for continuous scan
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
    2. Engineering
2. Hardware
  1. Emerging technologies
  2. Robustness

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Published In

DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 22 June 2001

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Chen JYang CLee K(2019)Test pattern generation and clock disabling for simultaneous test time and power reductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2002.80789022:3(363-370)Online publication date: 4-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2002.807890
Jin HWang YChen NWang SZeng L(2009)Predication of Program Behaviours for Functionality TestingProceedings of the 2009 First IEEE International Conference on Information Science and Engineering10.1109/ICISE.2009.843(4993-4996)Online publication date: 26-Dec-2009
https://dl.acm.org/doi/10.1109/ICISE.2009.843
Tehranipoor MAhmed N(2008)Testing SoC Interconnects for Signal IntegrityNanometer Technology Designs High-Quality Delay Tests10.1007/978-0-387-75728-5_12(241-275)Online publication date: 2008
https://doi.org/10.1007/978-0-387-75728-5_12
Ji-Jan Chen Kun-Lun Luo Yeong-Jar Chang Wen-Ching Wu (2005)Test pattern generation and clock disabling for test time and power reduction2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).10.1109/VDAT.2005.1500057(208-211)Online publication date: 2005
https://doi.org/10.1109/VDAT.2005.1500057
Fu YWang S(2005)Test Data Compression with Partial LFSR-ReseedingProceedings of the 14th Asian Test Symposium on Asian Test Symposium10.1109/ATS.2005.105(343-347)Online publication date: 18-Dec-2005
https://dl.acm.org/doi/10.1109/ATS.2005.105
Tehranipour MAhmed NNourani M(2003)Testing SoC interconnects for signal integrity using boundary scanProceedings. 21st VLSI Test Symposium, 2003.10.1109/VTEST.2003.1197647(158-163)Online publication date: 2003
https://doi.org/10.1109/VTEST.2003.1197647
Kuen-Jong Lee Jih-Jeen Chen (2002)Reducing test application time and power dissipation for scan-based testing via multiple clock disablingProceedings of the 11th Asian Test Symposium, 2002. (ATS '02).10.1109/ATS.2002.1181734(338-343)Online publication date: 2002
https://doi.org/10.1109/ATS.2002.1181734

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Interval Based X-Masking for Scan Compression Architectures

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Partial scan designs without using a separate scan clock

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