Article

L1 data cache decomposition for energy efficiency

Authors:

Michael Huang,

Jose Renau,

Seung-Moon Yoo,

Josep TorrellasAuthors Info & Claims

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

Pages 10 - 15

https://doi.org/10.1145/383082.383086

Published: 06 August 2001 Publication History

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References

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Cited By

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Lee EKang ILee SSuh GAhn JManne SHunter HAltman E(2019)TWiCeProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322232(385-396)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322232
Lee ELee SSuh GAhn J(2018)TWiCeIEEE Computer Architecture Letters10.1109/LCA.2017.278767417:1(96-99)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1109/LCA.2017.2787674
Kang SNicopoulos CGavrilovska AKim J(2015)Subtleties of Run-Time VirtualAddress StacksIEEE Computer Architecture Letters10.1109/LCA.2014.233729914:2(152-155)Online publication date: 1-Jul-2015
https://dl.acm.org/doi/10.1109/LCA.2014.2337299
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Index Terms

L1 data cache decomposition for energy efficiency
1. Hardware

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Published In

ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and design

August 2001

393 pages

ISBN:1581133715

DOI:10.1145/383082

Chairmen:
Enrico Macii
Politecnico di Torino, Turin, Italy
,
Vivek De
Intel Corporation, Hillsboro, OR
,
Mary Jane Irwin
Penn State Univ., University Park

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 August 2001

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ISLPED01: International Symposium on Low Power Electronics and Design

California, Huntington Beach, USA

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ISLPED '01 Paper Acceptance Rate 73 of 194 submissions, 38%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Lee EKang ILee SSuh GAhn JManne SHunter HAltman E(2019)TWiCeProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322232(385-396)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322232
Lee ELee SSuh GAhn J(2018)TWiCeIEEE Computer Architecture Letters10.1109/LCA.2017.278767417:1(96-99)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.1109/LCA.2017.2787674
Kang SNicopoulos CGavrilovska AKim J(2015)Subtleties of Run-Time VirtualAddress StacksIEEE Computer Architecture Letters10.1109/LCA.2014.233729914:2(152-155)Online publication date: 1-Jul-2015
https://dl.acm.org/doi/10.1109/LCA.2014.2337299
Chakraborty AHomayoun HKhajeh ADutt NEltawil AKurdahi F(2014)Multicopy CacheACM Transactions on Embedded Computing Systems10.1145/263216213:5s(1-27)Online publication date: 23-Jul-2014
https://dl.acm.org/doi/10.1145/2632162
Chen JVenkataramani GHuang H(2014)Exploring Dynamic Redundancy to Resuscitate Faulty PCM BlocksACM Journal on Emerging Technologies in Computing Systems10.1145/260215610:4(1-23)Online publication date: 2-Jun-2014
https://dl.acm.org/doi/10.1145/2602156
Grani PBartolini S(2014)Design Options for Optical Ring Interconnect in Future Client DevicesACM Journal on Emerging Technologies in Computing Systems10.1145/260215510:4(1-25)Online publication date: 2-Jun-2014
https://dl.acm.org/doi/10.1145/2602155
Lee STuck J(2013)Automatic parallelization of fine-grained metafunctions on a chip multiprocessorACM Transactions on Architecture and Code Optimization10.1145/2541228.254123710:4(1-26)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2541237
Rolán DFraguela BDoallo R(2013)Virtually split cacheACM Transactions on Architecture and Code Optimization10.1145/2541228.254123410:4(1-24)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2541234
Jantz MKulkarni P(2013)Exploring single and multilevel JIT compilation policy for modern machines 1ACM Transactions on Architecture and Code Optimization10.1145/2541228.254122910:4(1-29)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2541228.2541229
Abbaspour SBrandner FSchoeberl M(2013)A time-predictable stack cache16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)10.1109/ISORC.2013.6913225(1-8)Online publication date: Jun-2013
https://doi.org/10.1109/ISORC.2013.6913225
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Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems

Partitioned instruction cache architecture for energy efficiency

Energy-efficient synonym data detection and consistency for virtual cache