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Microassembly and area reduction techniques for PLA microcode

Authors:

Christos A. Papachriston,

James M. ReuterAuthors Info & Claims

ACM SIGMICRO Newsletter, Volume 15, Issue 4

Pages 86 - 94

https://doi.org/10.1145/384281.808218

Published: 01 December 1984 Publication History

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Abstract

This paper presents new techniques for generating PLA microcode with the overall goal of implementing functions or algorithms in VLSI. The microcode is appropriate for PLA-based microarchitectures with powerful sequencing capabilities already proposed. A microassembly language is introduced with unusual flexibility for conditional field assembly and capability to support microarchitectures based on PLA stores An important contribution of this work is an area reduction algorithm for PLA microcode based on a breadth-first graph searching approach. Experimental results provided demonstrate the viability and usefulness of the proposed technique for designing PLA firmware in a VLSI environment.

References

[1]

Brayton, R. et. al., "A Comparison of Logic Minimization Strategies using EXPRESSO: An APL Program Package for Partitioned Logic Minimization," Proceedings of the IEEE International Conference on Circuits and Computers, 1982.

Google Scholar

[2]

Chuquillanqui, S. and Perez-Segovia. T., "PAOLA: A Tool for Topological Optimization of Large PLAs," ACM IEEE Nineteenth Design Automation Conference Proceedings, pp. 300-306, 1982.

Digital Library

Google Scholar

[3]

Egan, J. and Liu, C., "Optimal Bipartite Folding of PLA," ACM IEEE Nineteenth Design Automation Conference Proceedings, pp. 141-146, 1982.

Digital Library

Google Scholar

[4]

Hatchel, G. et. al., "Techniques for Programmable Logic Array Folding," ACM IEEE Nineteenth Design Automation Conference Proceedings, pp. 147-155, 1982.

Digital Library

Google Scholar

[5]

Kang, S. and vanCleemput, W., "Automatic PLA Synthesis from a DDL-P Description," ACM IEEE Eighteenth Design Automation Conference Proceedings, pp. 391-397, 1981.

Digital Library

Google Scholar

[6]

Kernighan, B. and Ritchie, D., "The C Programming Language," Prentice Hall, 1978.

Digital Library

Google Scholar

[7]

Mick, J. and Brick, J., "Bit-Slice Microprocessor Design," McGraw Hill, 1980, pp. 168-175.

Digital Library

Google Scholar

[8]

Myers, G., "Digital System Design with LSI Bit-Slice Logic," John Wiley & Sons, 1980, pp. 300-322.

Digital Library

Google Scholar

[9]

Nilsson, N., "Principles of Artificial Intelligence," Tioga Publishing Company, 1980.

Digital Library

Google Scholar

[10]

Papachristou, C., "Hardware Microcontrol Schemes Using PLAs," Proc. 14th Annual IEEE Microprogramming Workshop, pp. 3-16, Dec. 1981.

Digital Library

Google Scholar

[11]

Papachristou, C. and Gambhir, S., "A Microsequencer Architecture with Firmware Support for Modular Microprogramming," Proc. 15th IEEE Microprogramming Workshop, pp. 105-113, Oct. 1982.

Digital Library

Google Scholar

[12]

Papachristou, C. and Gambhir, S., "A Bit-Slice Microcontrol Architecture for Structured Firmware Designs," IEEE 1983 International Workshop on Computer Systems Organization, pp. 154-163, March 1983.

Google Scholar

[13]

Reuter, J., "A Microassembler and PLA Compaction System for PLA Firmware," M.S. Thesis, University of Cincinnati, 1984.

Google Scholar

[14]

Ullman, J., "Computational Aspects of VLSI," Rockville, Maryland: Computer Science Press, 1984.

Digital Library

Google Scholar

Cited By

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Papachristou CPandya A(2006)A design scheme for PLA-based control tables with reduced area and time-delay costIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.551789:5(453-472)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.55178
Wei Zhao Papachristou C(1995)Architectural partitioning of control memory for application specific programmable processorsProceedings of IEEE International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD.1995.480166(521-526)Online publication date: 1995
https://doi.org/10.1109/ICCAD.1995.480166
Zhao WPapachristou CRudell R(1995)Architectural partitioning of control memory for application specific programmable processorsProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225105(521-526)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225105
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Microassembly and area reduction techniques for PLA microcode
1. Hardware

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Information

Published In

ACM SIGMICRO Newsletter Volume 15, Issue 4

MICRO 17: Proceedings of the Seventeenth Annual Microprogramming Workshop

Dec. 1984

302 pages

ISSN:1050-916X

DOI:10.1145/384281

Issue’s Table of Contents

MICRO 17: Proceedings of the 17th annual workshop on Microprogramming
December 1984
325 pages
Chairmen:
M. Carter,
R. A. Mueller

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 December 1984

Published in SIGMICRO Volume 15, Issue 4

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Cited By

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Papachristou CPandya A(2006)A design scheme for PLA-based control tables with reduced area and time-delay costIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.551789:5(453-472)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.55178
Wei Zhao Papachristou C(1995)Architectural partitioning of control memory for application specific programmable processorsProceedings of IEEE International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD.1995.480166(521-526)Online publication date: 1995
https://doi.org/10.1109/ICCAD.1995.480166
Zhao WPapachristou CRudell R(1995)Architectural partitioning of control memory for application specific programmable processorsProceedings of the 1995 IEEE/ACM international conference on Computer-aided design10.5555/224841.225105(521-526)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.5555/224841.225105
Tudruj MBelgard R(1985)A customized control store design in microprogrammed control unitsProceedings of the 18th annual workshop on Microprogramming10.1145/18927.18926(189-199)Online publication date: 1-Dec-1985
https://dl.acm.org/doi/10.1145/18927.18926
Tudruj M(1985)A customized control store design in microprogrammed control unitsACM SIGMICRO Newsletter10.1145/18906.1892616:4(189-199)Online publication date: 1-Dec-1985
https://dl.acm.org/doi/10.1145/18906.18926

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