Article

An optimal memory allocation for application-specific multiprocessor system-on-chip

Authors:

Ferid Gharsalli,

Frederic Rousseau,

Ahmed A. JerrayaAuthors Info & Claims

ISSS '01: Proceedings of the 14th international symposium on Systems synthesis

Pages 19 - 24

https://doi.org/10.1145/500001.500006

Published: 30 September 2001 Publication History

Abstract

In this paper, we present a novel and systematic approach for the design of shared memory architectures in the case of application-specific multiprocessor system-on-chip. This paper focuses on a memory allocation step which is based on an integer linear programming model. It permits to obtain an optimal distributed shared memory architecture minimizing the global cost to access the shared data in the application, and the memory cost. Our approach allows automatic generation of an architecture-level specification of the application. The effectiveness of this approach is illustrated by a packet routing switch example.

References

[1]

S.V Adve, V.S Pai, P. Ranganathan, "Recent Advances in Memory Consistency Models for Hardware Shared Memory Systems", Special issue on distributed Shared-Memory Systems, Mars 1999.

[2]

C. Amza, A. Cox, S. Dwarkadas, L. Jin & al, "Adaptive Protocols for Software Distributed Shared Memory", Special issue on distributed Shared-Memory Systems, Mars 1999.

[3]

A. Baghdadi, D. Lyonnard, N-E. Zergainoh, A.A. Jerraya, "An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC", Proc. of DATE 2001, Mar 2001.

Digital Library

[4]

F. Cathoor & al, Custom Memory Management Methodology, Kluwer Academic Publishers, 1998.

Digital Library

[5]

F. Cathoor, S. Wuytack & al, "System level transformations for low power data transfer and storage", in paper collection "low power CMOS design >>, IEEE Press, pp.609-618, 1998.

[6]

D. Culler, J.P. Singh, A. Gupta, "Parallel computer architecture :A Hardware/Software approach", Maurgan Kauffman publishers, August 1998.

Digital Library

[7]

K. Danckaert, F. Cathoor & al, "System-level memory optimization for hardware-software co-design", Proc. of Workshop on hardware/software co-design, Braunschweig, Germany, pp.55-59, March 1997.

Digital Library

[8]

L. Gauthier, S. Yoo, A.A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software", Proc. of DATE conference, Munich, March 2001.

Digital Library

[9]

J. Hennessy, M. Heinrich, A. Gupta, "Cache-Coherent Distributed Shared Memory : Perspectives on Its Development and Future Challenges", Special issue on distributed Shared-Memory Systems, March 1999.

[10]

IBM, Inc. "28.4G Packet Rooting Switch", Networking Technology Data sheets, http://www.chips.ibm.com/techlib/products/commun/datashe ets.html.

[11]

H.F. Leung, H.F. Ting, "An Optimal Algorithm for Global Termination Detection in Shared-Memory Asynchronous Multiprocessor Systems", IEEE Transactions on parallel and distributed systems, May 1997.

Digital Library

[12]

Y. Li, W. Wolf, "Allocation of Multirate Systems on Multiprocessors with Memory Hierarchy Modeling and Optimization", Proc. of CODES/CASHE '97, Braunschweig, Germany, March, 1997.

[13]

Y. Li, W. Wolf, "Hardware/Software Co-Synthesis with Memory Hierarchies", IEEE transaction on computer-aided design of integrated circuit and Systems, October 1999.

Digital Library

[14]

D. Lyonnard, S. Yoo, A. Baghdadi, A.A. Jerraya, "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip', Proc. of DAC 2001, June 2001, Las Vegas, Nevada, USA.

Digital Library

[15]

P. R. Panda, N. Dutt, A. Nicolau, Memory Issues in Embedded Systems-on-chip : Optimization and exploration, Kluwer Academic Publishers, 1999.

Digital Library

[16]

J. Protic, M. Tomasevic, V. Milutinovic, "Distributed Shared Memory : Concepts and Systems", IEEE Parallel & Distributed Technology; Summer 1996.

Digital Library

[17]

SystemC << user's manual >>, http://www.systemc.org.

[18]

S. Wuytack, J.P. Diguet & al, "Formalized methodology for data reuse exploration for low-power hierarchical memory mapping", IEEE Trans, on VLSI Systems, Vol6, 1998.

Digital Library

Cited By

OKI YABE YYAMAMOTO KYAMAMOTO KSHIRAKAWA TYOSHIDA AKIMURA KKASAHARA H(2020)Local Memory Mapping of Multicore Processors on an Automatic Parallelizing CompilerIEICE Transactions on Electronics10.1587/transele.2019LHP0010E103.C:3(98-109)Online publication date: 1-Mar-2020
https://doi.org/10.1587/transele.2019LHP0010
Bhat GSrinivas SChagari VPark JMcGiffen TLee HBliss DChakrabarti COgras U(2017)Fluid wireless protocolsProceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia10.1145/3139315.3139321(22-31)Online publication date: 15-Oct-2017
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https://dl.acm.org/doi/10.1109/TCAD.2016.2584048
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Published In

cover image ACM Conferences

ISSS '01: Proceedings of the 14th international symposium on Systems synthesis

September 2001

290 pages

ISBN:1581134185

DOI:10.1145/500001

General Chair:
Roman Hermida
Complutense Universidad, Madrid, Spain
,
Program Chair:
El Mostapha Aboulhamid
Université de Montréal, Québec, Canada

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE: IEEE Computer Society Technical Committee on Design Automation
SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 September 2001

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ISSS01: 14th International Symposium on System Synthesis

September 30 - October 3, 2001

P.Q., Montréal, Canada

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Overall Acceptance Rate 38 of 71 submissions, 54%

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Cited By

OKI YABE YYAMAMOTO KYAMAMOTO KSHIRAKAWA TYOSHIDA AKIMURA KKASAHARA H(2020)Local Memory Mapping of Multicore Processors on an Automatic Parallelizing CompilerIEICE Transactions on Electronics10.1587/transele.2019LHP0010E103.C:3(98-109)Online publication date: 1-Mar-2020
https://doi.org/10.1587/transele.2019LHP0010
Bhat GSrinivas SChagari VPark JMcGiffen TLee HBliss DChakrabarti COgras U(2017)Fluid wireless protocolsProceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia10.1145/3139315.3139321(22-31)Online publication date: 15-Oct-2017
https://dl.acm.org/doi/10.1145/3139315.3139321
Chang DLin IYong L(2017)ROHOMIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258404836:3(357-369)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2584048
Cilardo AFusella E(2016)Design automation for application-specific on-chip interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01752:C(102-121)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.017
Odendahl MGoens ALeupers RAscheid GHenriksson T(2015)Buffer Allocation Based On-Chip Memory Optimization for Many-Core PlatformsProceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop10.1109/IPDPSW.2015.67(1119-1124)Online publication date: 25-May-2015
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Odendahl MGoens ALeupers RAscheid GRies BVöcking BHenriksson TFettweis GNebel W(2014)Optimized buffer allocation in multicore platformsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617070(1-6)Online publication date: 24-Mar-2014
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Poorani AAnuradha BVivekanadhan C(2014)An effectual elucidation of task scheduling and memory partitioning for MPSoC2014 IEEE 8th International Conference on Intelligent Systems and Control (ISCO)10.1109/ISCO.2014.7103963(295-299)Online publication date: Jan-2014
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Leary GChe WChatha KGroeneveld PSciuto DHassoun S(2012)System-level synthesis of memory architecture for stream processing sub-systems of a MPSoCProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228481(672-677)Online publication date: 3-Jun-2012
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Li J(2011)BibliographyReal-Time Embedded Systems10.1201/b10935-12(187-207)Online publication date: 7-Jun-2011
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