Article

Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control

Authors:

Shantanu DuttAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 854 - 859

https://doi.org/10.1145/513918.514129

Published: 10 June 2002 Publication History

Abstract

This paper addresses the problem of tackling multiple constraints simultaneously during a partitioning driven placement (PDP) process, where a larger solution space is available for constraint-satisfying optimization compared to post placement methods. A general methodology of multi-constraint satisfaction that balances violation correction and primary optimization is presented. A number of techniques are introduced to ensure its convergence and enhance its solution search capability with intermediate relaxation. Application of our approach to congestion control modeled as pin density and external net distribution balance constraints shows it effectively reduces overall congestion by 14.3% and improves chip area by 8.9%, with reasonable running time and only 1.6% increase in wire length. As far as we know, this is the first time an approach to congestion reduction during placement optimization produced good congestion improvement with very small wire length increase.

References

[1]

A. E. Dunlop and B. W. Kernighan. A procedure for placement of standard-cell VLSI circuits. IEEE Trans. CAD, pp. 92--98, Jan. 1985

Digital Library

[2]

S. Dutt and W. Deng, "Probability-based Approaches to VLSI Circuit Partitioning," IEEE Trans. CAD, pp. 534--549, Mar. 2000

Digital Library

[3]

S. Dutt and H. Theny, "Partitioning Around Roadblocks: Tackling Constraints with Intermediate Relaxations", Proc. ICCAD, pp. 349--355, 1997

Digital Library

[4]

H. Eisenmann and F. M. Johannes, "Generic Global Placement and Floorplanning," Proc. DAC, pp. 269--274, 1998

Digital Library

[5]

H. Esbensen and E. Kuh, "Exploring the design space for building block placements considering area, aspect ratio, path delay and routing congestion", Proc. Physical Design Workshop, 1996, pp. 126--133

[6]

D. J-H. Huang and A.B. Kahng, "Partitioning-based standard-cell global placement with an exact objective", Proc. ISPD, pp. 18--25, 1997

Digital Library

[7]

R. Kuznar, F. Brglez and K. Kozminski, "Cost minimization of partitions into multiple devices", Proc. DAC, pp. 315--320, 1993

Digital Library

[8]

S. Mayrhofer and U. Lauther, "Congestion-driven placement using a new multi partitioning heuristic", Proc. ICCAD, pp. 332--335, 1990

[9]

P.N. Parakh, R.B. Brown and K.A. Sakallah, "Congestion-driven quadratic placement", Proc. DAC., pp. 275--258, 1998

Digital Library

[10]

W-J. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits", IEEE Trans. CAD, pp. 349--359, Mar. 1995

Digital Library

[11]

M. Wang, X. Yang and M. Sarrafzadeh, "Dragon2000: Fast Standard-cell Placement for Large Circuits", Proc. ICCAD, pp. 260--263, 2000

Digital Library

[12]

M. Wang, X. Yang and M. Sarrafzadeh, "Congestion Minimization During Placement", IEEE Trans. CAD, pp. 1140--1148, Oct. 2000

Digital Library

[13]

W. Wolf, Modern VLSI Design, 2nd ed., Prentice-Hall, 1998

Digital Library

[14]

X. Yang, R. Kastner and M. Sarrafzadeh, "Congestion Reduction During Placement Based on Integer Programming", Proc. ICCAD, pp. 573--576, 2001

Digital Library

[15]

K. Zhong and S. Dutt, "Effective partition-driven placement with simultaneous level processing and global net views", Proc. ICCAD, pp. 254--259, 2000

Digital Library

[16]

H. Zhou and D.F. Wong, "Global Routing with Crosstalk Constraints", Proc. DAC, pp. 374--377, 1998

Digital Library

Cited By

Chan WHo PKahng ASaxena POzdal MChu C(2017)Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine LearningProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036681(15-21)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036681
Markov IHu JKim MHu A(2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429441
Spindler PJohannes FLauwereins RMadsen J(2007)Fast and accurate routing demand estimation for efficient routability-driven placementProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266632(1226-1231)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266632
Show More Cited By

Index Terms

Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering

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cover image ACM Conferences

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Chan WHo PKahng ASaxena POzdal MChu C(2017)Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine LearningProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036681(15-21)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036681
Markov IHu JKim MHu A(2012)Progress and challenges in VLSI placement researchProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429441(275-282)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429441
Spindler PJohannes FLauwereins RMadsen J(2007)Fast and accurate routing demand estimation for efficient routability-driven placementProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266632(1226-1231)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266632
(2007)Congestion Optimization During PlacementRouting Congestion in VLSI Circuits: Estimation and Optimization10.1007/0-387-48550-3_5(145-188)Online publication date: 2007
https://doi.org/10.1007/0-387-48550-3_5
Selvakkumaran NParakh PKarypis GSylvester DStroobandt DScheffer LZarkesh-Ha P(2003)Perimeter-degreeProceedings of the 2003 international workshop on System-level interconnect prediction10.1145/639929.639941(53-59)Online publication date: 5-Apr-2003
https://dl.acm.org/doi/10.1145/639929.639941

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