Article

A framework for evaluating design tradeoffs in packet processing architectures

Authors:

Samarjit Chakraborty,

Matthias Gries,

Simon KünzliAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 880 - 885

https://doi.org/10.1145/513918.514136

Published: 10 June 2002 Publication History

Abstract

We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simulation, which tend to be infeasible when the design space is very large. We illustrate the feasibility of our method using a detailed case study.

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Cited By

Slomka FSadeghi M(2021)Beyond the limitations of real-time scheduling theory: a unified scheduling theory for the analysis of real-time systemsSICS Software-Intensive Cyber-Physical Systems10.1007/s00450-021-00429-1Online publication date: 29-Nov-2021
https://doi.org/10.1007/s00450-021-00429-1
Garay GTchernykh ADrozdov ANovikov SVladislavlev V(2016)A VHDL-Based Modeling of Network Interface Card Buffers: Design and Teaching MethodologyHigh Performance Computer Applications10.1007/978-3-319-32243-8_18(250-273)Online publication date: 8-Apr-2016
https://doi.org/10.1007/978-3-319-32243-8_18
Guan NYi WFettweis GNebel W(2014)General and efficient response time analysis for EDF schedulingProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616986(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616986
Show More Cited By

Index Terms

A framework for evaluating design tradeoffs in packet processing architectures
1. Computer systems organization
  1. Architectures
2. Hardware
  1. Communication hardware, interfaces and storage
  2. Electronic design automation
    1. Modeling and parameter extraction

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Published In

cover image ACM Conferences

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

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Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

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Cited By

Slomka FSadeghi M(2021)Beyond the limitations of real-time scheduling theory: a unified scheduling theory for the analysis of real-time systemsSICS Software-Intensive Cyber-Physical Systems10.1007/s00450-021-00429-1Online publication date: 29-Nov-2021
https://doi.org/10.1007/s00450-021-00429-1
Garay GTchernykh ADrozdov ANovikov SVladislavlev V(2016)A VHDL-Based Modeling of Network Interface Card Buffers: Design and Teaching MethodologyHigh Performance Computer Applications10.1007/978-3-319-32243-8_18(250-273)Online publication date: 8-Apr-2016
https://doi.org/10.1007/978-3-319-32243-8_18
Guan NYi WFettweis GNebel W(2014)General and efficient response time analysis for EDF schedulingProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616986(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616986
Garay GOrtega JDíaz ACorrales LAlarcón-Aquino V(2013)System performance evaluation by combining RTC and VHDL simulationJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.09.00659:10(1277-1298)Online publication date: 1-Nov-2013
https://dl.acm.org/doi/10.1016/j.sysarc.2013.09.006
Bacivarov IHaid WHuang KThiele L(2013)Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-ChipHandbook of Signal Processing Systems10.1007/978-1-4614-6859-2_27(867-903)Online publication date: 10-May-2013
https://doi.org/10.1007/978-1-4614-6859-2_27
Pollex VLipskoch HSlomka FKollmann SBoyer MFraboul CStea G(2011)Runtime improved computation of path latencies with the real-time calculusProceedings of the 1st International Workshop on Worst-Case Traversal Time10.1145/2071589.2071597(58-65)Online publication date: 29-Nov-2011
https://dl.acm.org/doi/10.1145/2071589.2071597
Baloukas CPapadopoulos LSoudris DStuijk SJovanovic OSchmoll FMarwedel PCordes DPyka RMallik AMamagkakis SCapman FCollet SMitas NKritharidis D(2011)Mapping Embedded Applications on MPSoCs: The MNEMEE ApproachVLSI 2010 Annual Symposium10.1007/978-94-007-1488-5_10(165-179)Online publication date: 8-Sep-2011
https://doi.org/10.1007/978-94-007-1488-5_10
Kempf TAscheid GLeupers RKempf TAscheid GLeupers R(2011)Related WorkMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_4(49-54)Online publication date: 10-Jan-2011
https://doi.org/10.1007/978-1-4419-8153-0_4
Lokuciejewski PPlazar SFalk HMarwedel PThiele L(2011)Approximating Pareto optimal compiler optimization sequences—a trade-off between WCET, ACET and code sizeSoftware—Practice & Experience10.1002/spe.107941:12(1437-1458)Online publication date: 1-Nov-2011
https://dl.acm.org/doi/10.1002/spe.1079
Bacivarov IHaid WHuang KThiele L(2010)Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-ChipHandbook of Signal Processing Systems10.1007/978-1-4419-6345-1_35(1007-1040)Online publication date: 16-Jul-2010
https://doi.org/10.1007/978-1-4419-6345-1_35
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