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Fractional rate dataflow model and efficient code synthesis for multimedia applications

Authors:

Hyunok Oh,

Soonhoi HaAuthors Info & Claims

ACM SIGPLAN Notices, Volume 37, Issue 7

Pages 12 - 17

https://doi.org/10.1145/566225.513834

Published: 19 June 2002 Publication History

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Abstract

Automatic code synthesis from dataflow program graphs is a promising high-level design methodology for rapid prototyping of multimedia embedded systems. Memory efficient code synthesis from dataflow models has been an active research subject to reduce the gap in terms of memory requirements between the synthesized code and the hand-optimized code. However, existent dataflow models have inherent difficulty of efficiently handling data structures. In this paper, we propose a new dataflow extension called fractional rate dataflow (FRDF) in which fractional number of samples can be produced and consumed. In the proposed FRDF model, a constituent data type is considered as a fraction of the composite data type. Existent integer rate dataflow models can be easily extended to incorporate the fractional rates without loosing analytical properties. In this paper, the SDF model is extended to include FRDF, which can reduce the buffer memory requirements significantly, up to 70%, for some multimedia applications.

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Cited By

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Jeong EJeong DHa S(2021)Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/344768026:5(1-38)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3447680
Lee YLiu YDesnos KBarford LBhattacharyya S(2020)Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing SystemsJournal of Signal Processing Systems10.1007/s11265-020-01581-892:10(1133-1151)Online publication date: 1-Oct-2020
https://dl.acm.org/doi/10.1007/s11265-020-01581-8
Honorat ADesnos KPelcat MNezan J(2019)Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_19(269-280)Online publication date: 7-Jul-2019
https://dl.acm.org/doi/10.1007/978-3-030-27562-4_19
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Index Terms

Fractional rate dataflow model and efficient code synthesis for multimedia applications
1. Computer systems organization
  1. Embedded and cyber-physical systems
  2. Real-time systems

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Information

Published In

ACM SIGPLAN Notices Volume 37, Issue 7

July 2002

232 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/566225

Issue’s Table of Contents

LCTES/SCOPES '02: Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
June 2002
244 pages
ISBN:1581135270
DOI:10.1145/513829
Conference Chairs:
Peter Marwedel
University of Dortmund
,
Srinivas Devadas
Massachusetts Institute of Technology

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 June 2002

Published in SIGPLAN Volume 37, Issue 7

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Cited By

View all

Jeong EJeong DHa S(2021)Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded SystemsACM Transactions on Design Automation of Electronic Systems10.1145/344768026:5(1-38)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3447680
Lee YLiu YDesnos KBarford LBhattacharyya S(2020)Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing SystemsJournal of Signal Processing Systems10.1007/s11265-020-01581-892:10(1133-1151)Online publication date: 1-Oct-2020
https://dl.acm.org/doi/10.1007/s11265-020-01581-8
Honorat ADesnos KPelcat MNezan J(2019)Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_19(269-280)Online publication date: 7-Jul-2019
https://dl.acm.org/doi/10.1007/978-3-030-27562-4_19
Liu YBarford LBhattacharyya S(2018)Generalized Graph Connections for Dataflow Modeling of DSP Applications2018 IEEE International Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2018.8598305(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/SiPS.2018.8598305
Honorat ATran HBesnard LGautier TTalpin JBouakaz ABini EPagetti C(2017)ADFGProceedings of the 25th International Conference on Real-Time Networks and Systems10.1145/3139258.3139267(158-167)Online publication date: 4-Oct-2017
https://dl.acm.org/doi/10.1145/3139258.3139267
Lesparre YMunier-Kordon ADelosme J(2016)Evaluation of Synchronous Dataflow Graph Mappings onto Distributed Memory Architectures2016 Euromicro Conference on Digital System Design (DSD)10.1109/DSD.2016.52(146-153)Online publication date: Aug-2016
https://doi.org/10.1109/DSD.2016.52
Lattuada MFerrandi F(2015)Modeling Resolution of Resources Contention in Synchronous Data Flow GraphsJournal of Signal Processing Systems10.1007/s11265-014-0923-y80:1(39-47)Online publication date: 1-Jul-2015
https://dl.acm.org/doi/10.1007/s11265-014-0923-y
Wu HShen CKee HSane NPlishker WBhattacharyya S(2014)Mapping Parameterized Dataflow Graphs onto FPGA PlatformsAcademic Press Library in Signal Processing: Volume 4 - Image, Video Processing and Analysis, Hardware, Audio, Acoustic and Speech Processing10.1016/B978-0-12-396501-1.00024-8(643-673)Online publication date: 2014
https://doi.org/10.1016/B978-0-12-396501-1.00024-8
Benazouz MMunier-Kordon ACorporaal HStuijk S(2013)Cyclo-static DataFlow phases scheduling optimization for buffer sizes minimizationProceedings of the 16th International Workshop on Software and Compilers for Embedded Systems10.1145/2463596.2463602(3-12)Online publication date: 19-Jun-2013
https://dl.acm.org/doi/10.1145/2463596.2463602
Ha SOh H(2011)Software synthesis in the ESL methodology for multicore embedded systems2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation10.1109/SAMOS.2011.6045484(355-362)Online publication date: Jul-2011
https://doi.org/10.1109/SAMOS.2011.6045484
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