Article

PipeRoute: a pipelining-aware router for FPGAs

Authors:

Akshay Sharma,

Carl Ebeling,

Scott HauckAuthors Info & Claims

FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

Pages 68 - 77

https://doi.org/10.1145/611817.611829

Published: 23 February 2003 Publication History

Get Access

Abstract

We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-Delay pipelined routing problem is to find the lowest cost route between a source and sink that goes through at least N (N > 1) distinct pipelining resources. In the case of a multi-terminal pipelined signal, the problem is to find a Minimum Spanning Tree that contains sufficient pipelining resources such that the delay constraint at each sink is satisfied. We begin this work by proving that the two terminal N-Delay problem is NP-Complete. We then propose an optimal algorithm for finding a lowest cost 1-Delay route. Next, the optimal 1-Delay router is used as the building block for a greedy two terminal N-Delay router. Finally, a multi-terminal routing algorithm (PipeRoute) that effectively leverages the 1-Delay and N-Delay routers is proposed. PipeRoute's performance is evaluated by routing a set of retimed benchmarks on the RaPiD [2] architecture. Our results show that the architecture overhead incurred in routing retimed netlists on RaPiD is less than a factor of two. Further, the results indicate a possible trend between the architecture overhead and the percentage of pipelined signals in a netlist.

References

[1]

V. Betz and J. Rose, "VPR: A New Packing, Placement and Routing Tool for FPGA Research," Seventh International Workshop on Field-Programmable Logic and Applications, pp 213--222, 1997.

Digital Library

Google Scholar

[2]

D. Cronquist, P. Franklin, C. Fisher, M. Figueroa, and C. Ebeling, "Architecture Design of Reconfigurable Pipelined Datapaths," Twentieth Anniversary Conference on Advanced Research in VLSI, pp 23--40, 1999.

Digital Library

Google Scholar

[3]

C. Ebeling, D. Cronquist, P. Franklin, "RaPiD - Reconfigurable Pipelined Datapath", 6th International Workshop on Field-Programmable Logic and Applications, pp 126--135, 1996.

Digital Library

Google Scholar

[4]

C. Leiserson, F. Rose, and J. Saxe, "Optimizing Synchronous Circuitry", Journal of VLSI and Computer Systems, pp 41--67, 1983.

Google Scholar

[5]

C. Leiserson, and J. Saxe, "Retiming Synchronous Circuitry", Algorithmica, 6(1):5--35, 1991.

Digital Library

Google Scholar

[6]

L. McMurchie and C. Ebeling, "PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs", ACM Third International Symposium on Field-Programmable Gate Arrays, pp 111--117, 1995.

Digital Library

Google Scholar

[7]

C. Sechen, VLSI Placement and Global Routing Using Simulated Annealing, Kluwer Academic Publishers, Boston, MA: 1988.

Google Scholar

[8]

A. Sharma, "Development of a Place and Route Tool for the RaPiD Architecture", Master's Project, University of Washington, December 2001.

Google Scholar

[9]

A. Sharma, C. Ebeling, S. Hauck, "PipeRoute: A Pipelining-Aware Router for FPGAs", University of Washington, Dept. of EE Technical Report UWEETR-0018, 2002.

Google Scholar

[10]

A. Singh, A. Mukherjee, M. Marek-Sadowska, "Interconnect Pipelining in a Throughput-Intensive FPGA Architecture", ACM/SIGDA Ninth International Symposium on Field-Programmable Gate Arrays, pp 153--160, 2001.

Digital Library

Google Scholar

[11]

D. Singh, S. Brown, "The Case for Registered Routing Switches in Field Programmable Gate Arrays", ACM/SIGDA Ninth International Symposium on Field-Programmable Gate Arrays, pp 161--169, 2001.

Digital Library

Google Scholar

[12]

D. Singh, S. Brown, "Integrated Retiming and Placement for Field Programmable Gate Arrays", Tenth ACM International Symposium on Field-Programmable Gate Arrays, pp 67--76, 2002.

Digital Library

Google Scholar

[13]

W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek and A. DeHon, "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array", ACM Seventh International Symposium on Field-Programmable Gate Arrays, 1999.

Digital Library

Google Scholar

Cited By

View all

Huang JLin CLiu YLi ZYang H(2014)Size aware placement for island style FPGAs2014 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2014.7082749(28-35)Online publication date: Dec-2014
https://doi.org/10.1109/FPT.2014.7082749
Teodorov CNarayanan PLagadec LDezan C(2011)Regular 2D NASIC-based architecture and design space explorationProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941486(70-77)Online publication date: 8-Jun-2011
https://dl.acm.org/doi/10.1109/NANOARCH.2011.5941486
So KHutton MChow P(2008)Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spiralsProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344677(24-34)Online publication date: 24-Feb-2008
https://dl.acm.org/doi/10.1145/1344671.1344677
Show More Cited By

Index Terms

PipeRoute: a pipelining-aware router for FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

Recommendations

PipeRoute: a pipelining-aware router for reconfigurable architectures

We present a pipelining-aware router for fieldprogrammable gate arrays (FPGAs). The problem of routing pipelined signals is different from the conventional FPGA routing problem. The two-terminal N_D pipelined routing problem is to find the lowest cost ...
A fast algorithm for computing minimum routing cost spanning trees

Communication networks have been developed based on two networking approaches: bridging and routing. The convergence to an all-Ethernet paradigm in Personal and Local Area Networks and the increasing heterogeneity found in these networks emphasizes the ...
Retiming synchronous circuitry
Abstract
This paper describes a circuit transformation calledretiming in which registers are added at some points in a circuit and removed from others in such a way that the functional behavior of the circuit as a whole is preserved. We show that retiming ...

Comments

Information & Contributors

Information

Published In

FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays

February 2003

256 pages

ISBN:158113651X

DOI:10.1145/611817

General Chair:
Steve Trimberger
Xilinx
,
Program Chair:
Russ Tessier
University of Massachusetts - Amherst

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 February 2003

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

FPGA03

Sponsor:

FPGA03: ACM/SIGDA International Symposium on Field Programmable Gate Arrays 2003

February 23 - 25, 2003

California, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
452
Total Downloads

Downloads (Last 12 months)8
Downloads (Last 6 weeks)3

Reflects downloads up to 11 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Huang JLin CLiu YLi ZYang H(2014)Size aware placement for island style FPGAs2014 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2014.7082749(28-35)Online publication date: Dec-2014
https://doi.org/10.1109/FPT.2014.7082749
Teodorov CNarayanan PLagadec LDezan C(2011)Regular 2D NASIC-based architecture and design space explorationProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941486(70-77)Online publication date: 8-Jun-2011
https://dl.acm.org/doi/10.1109/NANOARCH.2011.5941486
So KHutton MChow P(2008)Enforcing long-path timing closure for FPGA routing with path searches on clamped lexicographic spiralsProceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays10.1145/1344671.1344677(24-34)Online publication date: 24-Feb-2008
https://dl.acm.org/doi/10.1145/1344671.1344677
Compton KHauck S(2008)Automatic design of reconfigurable domain-specific flexible coresIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.91543916:5(493-503)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1109/TVLSI.2007.915439
So KMadden PPan D(2007)Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search spaceProceedings of the 2007 international symposium on Physical design10.1145/1231996.1232026(151-158)Online publication date: 18-Mar-2007
https://dl.acm.org/doi/10.1145/1231996.1232026
Eguro KHauck SWilton SDeHon A(2006)ArmadaProceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays10.1145/1117201.1117227(169-178)Online publication date: 22-Feb-2006
https://dl.acm.org/doi/10.1145/1117201.1117227
Bambha NBhattacharyya S(2005)Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2005.2016:2(99-112)Online publication date: 1-Feb-2005
https://dl.acm.org/doi/10.1109/TPDS.2005.20
Sharma ACompton KEbeling CHauck STessier RSchmit H(2004)Exploration of pipelined FPGA interconnect structuresProceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays10.1145/968280.968284(13-22)Online publication date: 22-Feb-2004
https://dl.acm.org/doi/10.1145/968280.968284
Song Li Ebeling C(2004)QuickRoute: a fast routing algorithm for pipelined architecturesProceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)10.1109/FPT.2004.1393253(73-80)Online publication date: 2004
https://doi.org/10.1109/FPT.2004.1393253

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

PipeRoute: a pipelining-aware router for reconfigurable architectures

A fast algorithm for computing minimum routing cost spanning trees

Retiming synchronous circuitry