Article

Understanding metrics in logic synthesis for routability enhancement

Authors:

Victor N. Kravets,

Prabhakar KudvaAuthors Info & Claims

SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction

Pages 3 - 5

https://doi.org/10.1145/639929.639931

Published: 05 April 2003 Publication History

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References

[1]

BRAYTON, R. K., AND MCMULLEN, C. The decomposition and factorization of Boolean expressions. In Proc. IEEE International Symposium on Circuits and Systems (May 1982), pp. 49--54.

Google Scholar

[2]

CHEN, Z., AND KOREN, I. Techniques for yield enhancement of VLSI adders. In International Conference on Application Specific Array Processors (1995), pp. 222--229.

Digital Library

Google Scholar

[3]

DONATH, W., KUDVA, P., STOK, L., VILLARRUBIA, P., REDDY, L., SULLIVAN, A., AND CHAKRABORTY, K. Transformational placement and synthesis. In Design Automation and Test in Europe (DATE) (Mar. 2000).

Digital Library

Google Scholar

[4]

HEINEKEN, H. T.,KHARE, J., MALY, W., NAG, P., OUYANG, C., AND W. A. PLESKACZ. Cad at the design-manufacturing interface. In Proc. ACM/IEEE Design Automation Conference (June 1997).

Digital Library

Google Scholar

[5]

HEINEKEN, H. T.,AND MALY, W. Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 1996), pp. 368--373.

Digital Library

Google Scholar

[6]

HUIJBREGTS, E. P., XUE, H., AND A. G. JESS. Routing for reliable manufacturing. IEEE Transactions On Semiconductor Manufacturing 8, 2 (Nov. 1995), 188--194.

Crossref

Google Scholar

[7]

KOREN, I., AND KOREN, Z. Incorporating yield enhancement into the floorplanning process. IEEE Transactions On Computers 49,6 (June 2000), 1--10.

Digital Library

Google Scholar

[8]

KRAVETS, V. N., AND SAKALLAH, K. A. Resynthesis of multi-level circuits under tight timing constraints. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 2002).

Digital Library

Google Scholar

[9]

KUDVA, P., SULLIVAN, A., AND DOUGHERTY, W. Metrics for structural logic synthesis. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 2002).

Digital Library

Google Scholar

[10]

MALY, W., HEINEKEN, H., J. KHARE, AND P. K. NAG. Design for manufacturability in submicron domain. In Proc. International Conf. Computer-Aided Design (ICCAD) (Nov. 1996).

Digital Library

Google Scholar

[11]

R. K. PRASAD, AND I. KOREN. The effect of placement on yield for standard cell designs. In Proceedings of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Oct. 2000), pp. 3--11.

Digital Library

Google Scholar

[12]

SENTOVICH, E. M. SIS: A system for sequential circuit synthesis. Tech. Rep. UCB/ERL M92/41, UC Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

Google Scholar

[13]

VENKATARAMAN, A., AND KOREN, I. Determination of yield bounds prior to routing. In Proceedings of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Nov. 1999), pp. 4--13.

Digital Library

Google Scholar

[14]

YANG, S. Logic synthesis and optimization benchmarks user guide-version 3.0. Microelectronics Center of North Carolina, Research Triangle Park, NC, Jan. 1991.

Google Scholar

Cited By

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Liu HRajavel SAkoglu A(2013)Integration of Net-Length Factor with Timing- and Routability-Driven Clustering AlgorithmsACM Transactions on Reconfigurable Technology and Systems10.1145/25173246:3(1-21)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1145/2517324
Fischbach RLienig JMeister TCheng CReda S(2009)From 3D circuit technologies and data structures to interconnect predictionProceedings of the 11th international workshop on System level interconnect prediction10.1145/1572471.1572485(77-84)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1572471.1572485
Pandit AAkoglu A(2007)Wirelength Prediction for FPGAs2007 International Conference on Field Programmable Logic and Applications10.1109/FPL.2007.4380760(749-752)Online publication date: Aug-2007
https://doi.org/10.1109/FPL.2007.4380760
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Index Terms

Understanding metrics in logic synthesis for routability enhancement
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
      1. Circuit optimization

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Published In

SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction

April 2003

147 pages

ISBN:1581136277

DOI:10.1145/639929

General Chair:
Dennis Sylvester
University of Michigan, Ann Arbor, MI
,
Program Chairs:
Dirk Stroobandt
Ghent University, Belgium
,
Lou Scheffer
Cadence
,
Publications Chair:
Payman Zarkesh-Ha
LSI Logic

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 April 2003

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SLIP03

Sponsor:

SLIP03: International Workshop on System Level Interconnect Prediction

April 5 - 6, 2003

CA, Monterey, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Cited By

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Liu HRajavel SAkoglu A(2013)Integration of Net-Length Factor with Timing- and Routability-Driven Clustering AlgorithmsACM Transactions on Reconfigurable Technology and Systems10.1145/25173246:3(1-21)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1145/2517324
Fischbach RLienig JMeister TCheng CReda S(2009)From 3D circuit technologies and data structures to interconnect predictionProceedings of the 11th international workshop on System level interconnect prediction10.1145/1572471.1572485(77-84)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1572471.1572485
Pandit AAkoglu A(2007)Wirelength Prediction for FPGAs2007 International Conference on Field Programmable Logic and Applications10.1109/FPL.2007.4380760(749-752)Online publication date: Aug-2007
https://doi.org/10.1109/FPL.2007.4380760
(2007)Congestion Optimization During Technology Mapping and Logic SynthesisRouting Congestion in VLSI Circuits: Estimation and Optimization10.1007/0-387-48550-3_6(189-229)Online publication date: 2007
https://doi.org/10.1007/0-387-48550-3_6
(2007)Synthesis-level Metrics for Routing CongestionRouting Congestion in VLSI Circuits: Estimation and Optimization10.1007/0-387-48550-3_3(67-94)Online publication date: 2007
https://doi.org/10.1007/0-387-48550-3_3
Liu QMarek-Sadowska M(2006)Semi-individual wire-length prediction with application to logic synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85948725:4(611-624)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.859487
Liu QMarek-Sadowska MGroeneveld PScheffer L(2005)Wire length prediction-based technology mapping and fanout optimizationProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055167(145-151)Online publication date: 3-Apr-2005
https://dl.acm.org/doi/10.1145/1055137.1055167
Lembach RArce-Nazario REisenmenger DWood CGroeneveld PScheffer L(2005)A diagnostic method for detecting and assessing the impact of physical design optimizations on routingProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055141(2-6)Online publication date: 3-Apr-2005
https://dl.acm.org/doi/10.1145/1055137.1055141
Liu QMarek-Sadowska MMalik SFix LKahng A(2004)Pre-layout wire length and congestion estimationProceedings of the 41st annual Design Automation Conference10.1145/996566.996726(582-587)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996726

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