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RISC watch

Published: 01 March 1984 Publication History
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References

[1]
J.K. Ousterhout, "Crystal: A Timing Analyzer for nMOS VLSI Circuits," Proc. Third Caltech Conference on Very Large Scale Integration, pp. 57--70, 1983.
[2]
R.W. Sherburne, M.G.H. Katevenis, D.A. Patterson, and C.H. Séquin, "A 32b NMOS Microprocessor with a Large Register File," 31st International Solid States Circuit Conference, San Francisco, February 23--25, 1984.
[3]
T. Sippel, "Floating RISCs," M.S. Project Report, U.C. Berkeley, September 1982. (Unpublished)
[4]
F. Ware, "Pipelined IEEE Floating Point Processor," Compcon, February 28-March 3, 1984.
[5]
H.J. Curnow and B.A. Wichmann, "A Synthetic Benchmark," Computer Journal, vol. 19, no. 1, 1975.
[6]
B.A. Wichmann and H.J. Curnow, "The Design of Synthetic Programs," in Benchmarking: Computer Evaluation and Measurement, pp. 89--114, John Wiley & Sons, London, 1975.
[7]
J.W. Verity, "Minis Lose out to PCs," Datamation, vol. 29, no. 11, pp. 44--52, November 1983.
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J. Miros, "A C Compiler for RISC I," M.S. Project Report, U.C. Berkeley, September 1982. (Unpublished)
[9]
C. Ponder, ". but will RISC run LISP? (a feasibility study)," Computer Science Technical Report No. UCB/CSD 83/122, U.C. Berkeley, August 1983. M.S. Project Report.
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R. Blomseth, "A Big RISC," Computer Science Technical Report No. UCB/CSD 83/143, U.C. Berkeley, November 1983. M.S. Project Report.
[11]
J.B. Peek, "The VLSI Circuitry of RISC I," Computer Science Technical Report No. UCB/CSD 83/135, U.C. Berkeley, June 1983. M.S. Project Report.
[12]
M.G.H. Katevenis, "Reduced Instruction Set Computer Architectures for VLSI," Computer Science Technical Report No. UCB/CSD 83/141, U.C. Berkeley, October, 1983. PhD Dissertation.
[13]
R.W. Sherburne, Processor Design Tradeoffs in VLSI, U.C. Berkeley, May, 1984. PhD Dissertation (in preparation).
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J. Hennessy, N. Jouppi, F. Baskett, A. Strong, T. Gross, C. Rowen, and J. Gill, "The MIPS Machine," Proc. Compcon, pp. 1--7, San Francisco, California, February 1982.
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G. Radin, "The 801 Minicomputer," Proc. Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 39--47, Palo Alto, California, March 1--3, 1982.
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D.A. Patterson and R.S. Piepho, "RISC Assessment: A High-Level Language Experiment," Proc. Ninth International Symposium on Computer Architecture, Austin, Texas, April 26--29, 1982.
[17]
F.C. Chow, "A Portable Machine-Independent Global Optimizer---Design and Measurements," Computer Systems Laboratory Technical Note No. 83--254, Stanford University, December, 1983. PhD Dissertation
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D. Folger and E. Basart, "Computer Architectures -- Designing for Speed," Compcon, pp. 25--31, February 28-March 3, 1983.
[19]
R. Ragan-Kelley, "Performance of the Pyramid Computer," Compcon, February 28-March 1, 1983.
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I. Barron, P. Cavill, D. May, and P. Wilson, "Transputer does 5 or more MIPS even when not used in parallel," Electronics, pp. 109--115., November 17, 1983.
[21]
C. Barney, "Fewer Instructions Speed Up VLSI," Electronics, vol. 55, no. 23, pp. 101--102, November 17, 1983.
[22]
B. Supnik and I. Evans, "MicroVAX 32 -- A VAX-Compatible Microprocessor," Compcon, February 28-March 3, 1984.
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S.J. Metz, "Letter to the Editor," Computer Architecture News, vol. 11, no. 5, December 1983.
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J. Beck, D. Dobberpuhl, M.J. Doherty, E. Dorenkamp, R. Grondalski, D. Grondalski, K. Henry, M. Miller, R. Supnik, S. Thierauf, and R. Witek, "A 32b Microprocessor with On-Chip Virtual Memory Management," 31st International Solid States Circuit Conference, San Francisco, February 23--25, 1984.
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      cover image ACM SIGARCH Computer Architecture News
      ACM SIGARCH Computer Architecture News  Volume 12, Issue 1
      March 1984
      70 pages
      ISSN:0163-5964
      DOI:10.1145/641602
      Issue’s Table of Contents

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 01 March 1984
      Published in SIGARCH Volume 12, Issue 1

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      • (1995)A trace-driven simulation methodologyACM SIGARCH Computer Architecture News10.1145/218328.21834323:5(27-33)Online publication date: 15-Dec-1995
      • (1995)A performance evaluation methodology for computer systemsProceedings International Phoenix Conference on Computers and Communications10.1109/PCCC.1995.472415(713-719)Online publication date: 1995
      • (1994)A methodology for evaluating the performance of CISC computer systems under single and two-level cache environmentsMicroprocessing and Microprogramming10.1016/0165-6074(94)90106-640:6(411-426)Online publication date: 1-Jul-1994
      • (1991)A methodology for evaluating the performance of RISC processors[Proceedings] 1991 Symposium on Applied Computing10.1109/SOAC.1991.143877(213-222)Online publication date: 1991
      • (1988)Reduced instruction set computer architectureProceedings of the IEEE10.1109/5.328776:1(38-55)Online publication date: Jan-1988
      • (1988)Integer Multiplication and Division on the HP Precision ArchitectureIEEE Transactions on Computers10.1109/12.224837:8(980-990)Online publication date: 1-Aug-1988
      • (1988)Floating point arithmetic on a RISCMicroprocessing and Microprogramming10.1016/0165-6074(88)90352-323:1-5(179-184)Online publication date: 1-Mar-1988
      • (1987)Integer multiplication and division on the HP precision architectureProceedings of the second international conference on Architectual support for programming languages and operating systems10.1145/36206.36189(90-99)Online publication date: 1-Oct-1987
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