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Efficient synchronization primitives for large-scale cache-coherent multiprocessors

Authors:

James R. Goodman,

Mary K. Vernon,

Philip J. WoestAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 17, Issue 2

Pages 64 - 75

https://doi.org/10.1145/68182.68188

Published: 01 April 1989 Publication History

Abstract

This paper proposes a set of efficient primitives for process synchronization in multiprocessors. The only assumptions made in developing the set of primitives are that hardware combining is not implemented in the inter-connect, and (in one case) that the interconnect supports broadcast.

The primitives make use of synchronization bits (syncbits) to provide a simple mechanism for mutual exclusion. The proposed implementation of the primitives includes efficient (i.e. local) busy-waiting for syncbits. In addition, a hardware-supported mechanism for maintaining a first-come first-serve queue of requests for a syncbit is proposed. This queueing mechanism allows for a very efficient implementation of, as well as fair access to, binary semaphores. We also propose to implement Fetch and Add with combining in software rather than hardware. This allows an architecture to scale to a large number of processors while avoiding the cost of hardware combining.

Scenarios for common synchronization events such as work queues and barriers are presented to demonstrate the generality and ease of use of the proposed primitives. The efficient implementation of the primitives is simpler if the multiprocessor has a hardware cache-consistency protocol. To illustrate this point, we outline how the primitives would be implemented in the Multicube multiprocessor [GoWo88].

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Efficient synchronization primitives for large-scale cache-coherent multiprocessors
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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 17, Issue 2

Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems

April 1989

291 pages

ISSN:0163-5964

DOI:10.1145/68182

Editor:
Joel Emer

Issue’s Table of Contents

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems
April 1989
303 pages
ISBN:0897913000
DOI:10.1145/70082
Chairman:
Joel Emer,
General Chair:
John Hennessy
Stanford University

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 April 1989

Published in SIGARCH Volume 17, Issue 2

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Feldmann MScheideler CScheideler CBerenbrink P(2019)Skeap & SeapThe 31st ACM Symposium on Parallelism in Algorithms and Architectures10.1145/3323165.3323193(287-296)Online publication date: 17-Jun-2019
https://dl.acm.org/doi/10.1145/3323165.3323193
Yi ZChen FYao Y(2019)A barrier optimization framework for NUMA multi‐core systemConcurrency and Computation: Practice and Experience10.1002/cpe.552732:5Online publication date: 21-Oct-2019
https://doi.org/10.1002/cpe.5527
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https://dl.acm.org/doi/10.1145/3132168
Haider SHasenplaugh WAlistarh D(2016)Lease/releaseACM SIGPLAN Notices10.1145/3016078.285115551:8(1-12)Online publication date: 27-Feb-2016
https://dl.acm.org/doi/10.1145/3016078.2851155
Haider SHasenplaugh WAlistarh DAsenjo RHarris T(2016)Lease/releaseProceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/2851141.2851155(1-12)Online publication date: 27-Feb-2016
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Chen JDong Y(2012)Energy optimization of representative barrier algorithmsJournal of Central South University10.1007/s11771-012-1348-z19:10(2823-2831)Online publication date: 4-Oct-2012
https://doi.org/10.1007/s11771-012-1348-z
Sahelices Bde Dios AIbáñez PViñals-Yúfera VLlabería J(2012)Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence ControllersJournal of Computer Science and Technology10.1007/s11390-012-1207-227:1(75-91)Online publication date: 9-Jan-2012
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Ellen FRamachandran VWoelfel P(2012)Efficient fetch-and-incrementProceedings of the 26th international conference on Distributed Computing10.1007/978-3-642-33651-5_2(16-30)Online publication date: 16-Oct-2012
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Hnat TWhitehouse K(2010)A relaxed synchronization primitive for macroprogramming systems2010 Seventh International Conference on Networked Sensing Systems (INSS)10.1109/INSS.2010.5573561(219-226)Online publication date: Jun-2010
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