Data buffering: run-time versus compile-time support
Author: 
H. MulderAuthors Info & Claims
H. MulderAuthors Info & ClaimsPages 144 - 151
Abstract
Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).
A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion
References
[1]
Johannes M. Mulder. Tradeoffs in Processor-Architecture and Data-Bui~er Design. techzeport 345, Stanford University, December 1987.
[2]
M. J. Flynn, C.L. Mitchel, and J.M. Mulder. And now a case for more complex instructions. IEEE, Computer, 20(9):71- 83~ September 1987.
[3]
D. A. Patterson and C.H. Sequin. RISC h a reduced instruction set VLSI computer. In Proceedings o/the Eight International Symposium on Oomputer Architecture, IEEE and ACM, May 1981.
[4]
Manolis G.H. Katevenis. Reduced Instruction Set Computes' Architectures for VLSL PhD thesis, Computer Science Division (EECS), University of California Berkeley, October 1983.
[5]
Daniel C. Halbert and Peter B. Kessler. Windows of Over. lapping Register Frames. Technical Report, Computer Science Division, University of California Berkeley, California 94720, 1980.
[6]
A. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, 1986.
[7]
Gregory J. Chsitin, Marc A. Auslander, Ashok K. Chandra, John Cocke, Martin E. Hopkins, and Peter W. Markstein. Register allocation via coloring. Computer Languages, 6:47- 57, 1981.
[8]
David R. Ditzel and H. R. McLellan. Register allocation for free: The C Machine stack cache. In Proceedings, Symposium on Architectural Support for Programming Languages and Operating Systems, pages 48-56, March 1982.
[9]
A.D. Berenbaum, D.IL Ditzel, and H.R. Mclellan. Introduction to the CRISP instruction set architecture. In Proceed. ings of COMPCON 1987, pages 86-90, January 1987.
[10]
Sumit Bandyopadhyay, Vimal S. Begwani, and Robert B. Murray. Compiling for the crisp microprocessor. In Proceedings o! COMPC'ON 1987, pages 96-I00, January 1987.
[11]
Donald Alpert. Memory Hierarchies .for Directly Ezeeuted Language Microprocessors. Technical Report 84-260, Computer Systems Laboratory, Stanford University, Stanford, California 94305, June 1984.
[12]
Frederick C. Chow. A Portable Machine-Independent Global Optimizer- Design and Measurements. PhD thesis, Computer Systems Laboratory, Department of Electrical Engineering and Computer Science, Stanford University, Stun. ford, December 1983.
[13]
Peter Nye. U-Code An intermediate Language for PascalS and Fortran. S-1 Document PAIL-8, Stanford University, May 1982.
[14]
D. Wall. Global register allocation at link time. In Proceed. ings o! the SIGPLAN'86 Symposium on Compiler Construction, pages 264-275, ACM, June 1986.
[15]
P. A. $teenkiste. LISP on a Reduced-Instruction-Set Proces. sot: Characterization and Optimization. PhD thesis, Computer Systems Laboratory, Stanford University, March 1987.
[16]
David W. Wall. Register windows vs. register allocation. In Proceedingz, Conference on Language Design and lmplementation, pages 67-78, June 1988.
Index Terms
- Data buffering: run-time versus compile-time support
Recommendations
Data buffering: run-time versus compile-time support
ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systemsData-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local ...
Run-time versus compile-time instruction scheduling in superscalar (RISC) processors: performance and tradeoffs
HIPC '96: Proceedings of the Third International Conference on High-Performance Computing (HiPC '96)The RISC revolution has spurred the development of processors with increasing degrees of instruction level parallelism (ILP). In order to realize the full potential of these processors, multiple instructions must continuously be issued and executed in a ...
Comments
Information & Contributors
Information
Published In
Copyright © 1989 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 01 April 1989
Published in SIGARCH Volume 17, Issue 2
Check for updates
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations7Total Citations
- 685Total Downloads
- Downloads (Last 12 months)401
- Downloads (Last 6 weeks)6
Reflects downloads up to 11 Aug 2024
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in