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Limits on multiple instruction issue

Authors:

M. Johnson, and

M. A. HorowitzAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 17, Issue 2

Pages 290 - 302

https://doi.org/10.1145/68182.68209

Published: 01 April 1989 Publication History

Abstract

This paper investigates the limitations on designing a processor which can sustain an execution rate of greater than one instruction per cycle on highly-optimized, non-scientific applications. We have used trace-driven simulations to determine that these applications contain enough instruction independence to sustain an instruction rate of about two instructions per cycle. In a straightforward implementation, cost considerations argue strongly against decoding more than two instructions in one cycle. Given this constraint, the efficiency in instruction fetching rather than the complexity of the execution hardware limits the concurrency attainable at the instruction level.

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Cited By

Stefanović DMartonosi M(2000)Limits and Graph Structure of Available Instruction-Level ParallelismEuro-Par 2000 Parallel Processing10.1007/3-540-44520-X_144(1018-1022)Online publication date: 18-Aug-2000
https://doi.org/10.1007/3-540-44520-X_144
Skadron KAhuja PMartonosi MClark D(1999)Branch Prediction, Instruction-Window Size, and Cache SizeIEEE Transactions on Computers10.1109/12.81111548:11(1260-1281)Online publication date: 1-Nov-1999
https://dl.acm.org/doi/10.1109/12.811115
Wallace SBagherzadeh N(1998)Modeled and Measured Instruction Fetching Performance for Superscalar MicroprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.6894449:6(570-578)Online publication date: 1-Jun-1998
https://dl.acm.org/doi/10.1109/71.689444
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Limits on multiple instruction issue

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 17, Issue 2

Special issue: Proceedings of ASPLOS-III: the third international conference on architecture support for programming languages and operating systems

April 1989

291 pages

ISSN:0163-5964

DOI:10.1145/68182

Editor:
Joel Emer

Issue’s Table of Contents

ASPLOS III: Proceedings of the third international conference on Architectural support for programming languages and operating systems
April 1989
303 pages
ISBN:0897913000
DOI:10.1145/70082
Chairman:
Joel Emer,
General Chair:
John Hennessy
Stanford University

Copyright © 1989 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

Published in SIGARCH Volume 17, Issue 2

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Cited By

Stefanović DMartonosi M(2000)Limits and Graph Structure of Available Instruction-Level ParallelismEuro-Par 2000 Parallel Processing10.1007/3-540-44520-X_144(1018-1022)Online publication date: 18-Aug-2000
https://doi.org/10.1007/3-540-44520-X_144
Skadron KAhuja PMartonosi MClark D(1999)Branch Prediction, Instruction-Window Size, and Cache SizeIEEE Transactions on Computers10.1109/12.81111548:11(1260-1281)Online publication date: 1-Nov-1999
https://dl.acm.org/doi/10.1109/12.811115
Wallace SBagherzadeh N(1998)Modeled and Measured Instruction Fetching Performance for Superscalar MicroprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.6894449:6(570-578)Online publication date: 1-Jun-1998
https://dl.acm.org/doi/10.1109/71.689444
Gonzalez RHorowitz M(1996)Energy dissipation in general purpose microprocessorsIEEE Journal of Solid-State Circuits10.1109/4.53541131:9(1277-1284)Online publication date: Jan-1996
https://doi.org/10.1109/4.535411
Chang MLai F(1996)Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File SchemeIEEE Transactions on Computers10.1109/12.48556745:3(278-293)Online publication date: 1-Mar-1996
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Warter NChang PMahlke SChen WHwu W(1995)Three Architectural Models for Compiler-Controlled Speculative ExecutionIEEE Transactions on Computers10.1109/12.37616444:4(481-494)Online publication date: 1-Apr-1995
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Hu XBurgstaller BScholz B(2023)EVMTracer: Dynamic Analysis of the Parallelization and Redundancy Potential in the Ethereum Virtual MachineIEEE Access10.1109/ACCESS.2023.326727711(47159-47178)Online publication date: 2023
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Chien ELevi ZWeber O(2016)Bounded distortion parametrization in the space of metricsACM Transactions on Graphics10.1145/2980179.298242635:6(1-16)Online publication date: 5-Dec-2016
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