Article

A novel 32-bit scalable multiplier architecture

Authors:

Yeshwant Kolla,

Yong-Bin Kim,

John CarterAuthors Info & Claims

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

Pages 241 - 244

https://doi.org/10.1145/764808.764871

Published: 28 April 2003 Publication History

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Abstract

In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable to higher-order multiplication. This multiplier topology is highly conducive for an electronic design automation (EDA) tool based implementation. A 32-bit version of this multiplier has been implemented using a standard ASIC design methodology and one variation of the standard design methodology in a 0.25μm technology. This 32-bit multiplier has a latency of 3.56ns.

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L. Dadda. Some schemes for parallel multipliers. Alta Frequenza 34(5):349--356, March 1965.

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M. Santoro. Design and clocking of vlsi multipliers. Ph. D. thesis, Stanford University October 1989.

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C. Wallace. A suggestion for fast multipliers. IEEE Transactions on electronic Computers EC(13):14--17, February 1964.

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Vaidya SDandekar DJena SKumar RTuruk ADash M(2011)A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematicsProceedings of the 2011 International Conference on Communication, Computing & Security10.1145/1947940.1948020(383-386)Online publication date: 12-Feb-2011
https://dl.acm.org/doi/10.1145/1947940.1948020
Zhou Shun Pfander OPfleiderer HBermak A(2007)A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier2007 14th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2007.4511155(975-978)Online publication date: Dec-2007
https://doi.org/10.1109/ICECS.2007.4511155

Index Terms

A novel 32-bit scalable multiplier architecture
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

April 2003

320 pages

ISBN:1581136773

DOI:10.1145/764808

General Chair:
Mircea Stan
University of Virginia
,
Program Chairs:
David Garrett
Bell Labs Research, Lucent Technologies
,
Kazuo Nakajima
University of Maryland

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 28 April 2003

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GLSVLSI03: Great Lakes Symposium on VLSI 2003

April 28 - 29, 2003

D. C., Washington, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Vaidya SDandekar DJena SKumar RTuruk ADash M(2011)A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematicsProceedings of the 2011 International Conference on Communication, Computing & Security10.1145/1947940.1948020(383-386)Online publication date: 12-Feb-2011
https://dl.acm.org/doi/10.1145/1947940.1948020
Zhou Shun Pfander OPfleiderer HBermak A(2007)A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier2007 14th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2007.4511155(975-978)Online publication date: Dec-2007
https://doi.org/10.1109/ICECS.2007.4511155

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A Novel Signed Array Multiplier

A High-speed 32-bit Signed/Unsigned Pipelined Multiplier

A Parallel-Serial Decimal Multiplier Architecture

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A Novel Signed Array Multiplier

A High-speed 32-bit Signed/Unsigned Pipelined Multiplier

A Parallel-Serial Decimal Multiplier Architecture

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