While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

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Almawzan RParia SDasgupta AAmberiadis KBhunia S(2024)IP Security in Structured ASIC: Challenges and Prospects2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00078(397-402)Online publication date: 1-Jul-2024
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Emmert JPerumalla AHudson TConcha L(2022)THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.316842069:7(2906-2915)Online publication date: Jul-2022
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Index Terms

Exploring regular fabrics to optimize the performance-cost trade-off
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design
    1. Application-specific VLSI designs

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DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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https://doi.org/10.1109/ISVLSI61997.2024.00078
Hu JKahng A(2023)Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323684(1-7)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323684
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https://doi.org/10.1109/TCSI.2022.3168420
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Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage

Effect of Process Variation on Power and Delay in CMOS Circuits

Design benchmarking to 7nm with FinFET predictive technology models

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