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Towards efficient fine-grain software pipelining

Authors:

Herbert H. J. Hum,

Yue-Bong WongAuthors Info & Claims

ICS '90: Proceedings of the 4th international conference on Supercomputing

Pages 369 - 379

https://doi.org/10.1145/77726.255177

Published: 01 June 1990 Publication History

Abstract

Dataflow software pipelining was proposed as a means of structuring fine-grain parallelism and has been studied mostly under an idealized dataflow architecture model with infinite resources[9]. In this paper, we investigate the effects of software pipelining under realistic architecture models with finite resources. Our target architecture is the McGill Dataflow Architecture which employs conventional pipelined techniques to achieve fast instruction execution, while exploiting fine-grain parallelism via a data-driven instruction scheduler. To achieve optimal execution efficiency, the compiled code must be able to make a balanced use of both the parallelism in the instruction execution unit and the fine-grain synchronization power of the machine.

A detailed analysis based on simulation results is presented, focusing on two key architectural factors - the fine-grain synchronization capacity and the scheduling mechanism for enabling instructions. On one hand, our results provide experimental evidence that software pipelining is an effective method for exploiting fine-grain parallelism in loops. On the other, the experiments have also revealed the (somewhat pessimistic) fact that even a fully software pipelined code may not achieve good performance if the overhead for fine-grain synchronization exceeds the capacity of the machine.

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Cited By

Hum HGao G(2005)A novel high-speed memory organization for fine-grain multi-thread computingPARLE '91 Parallel Architectures and Languages Europe10.1007/BFb0035095(34-51)Online publication date: 23-Jun-2005
https://doi.org/10.1007/BFb0035095
Ning QGao G(2005)Minimizing loop storage allocation for an argument-fetching dataflow architecture modelPARLE '92 Parallel Architectures and Languages Europe10.1007/3-540-55599-4_112(585-600)Online publication date: 14-Jul-2005
https://doi.org/10.1007/3-540-55599-4_112
Gao GHum HWong Y(2005)An efficient scheme for fine-grain software pipeliningCONPAR 90 — VAPP IV10.1007/3-540-53065-7_147(709-720)Online publication date: 2-Jun-2005
https://doi.org/10.1007/3-540-53065-7_147
Show More Cited By

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Published In

cover image ACM Conferences

ICS '90: Proceedings of the 4th international conference on Supercomputing

June 1990

492 pages

ISBN:0897913698

DOI:10.1145/77726

Chairmen:
Ahmed Sameh
Univ. of Illinois
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands

ACM SIGARCH Computer Architecture News Volume 18, Issue 3b
Special Issue: Proceedings of the 4th international conference on Supercomputing
Sept. 1990
489 pages
ISSN:0163-5964
DOI:10.1145/255129
Chairmen:
Ahmed Sameh
Univ. of Illinois at Urbana-Champaign, Urbana
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands
Issue’s Table of Contents

Copyright © 1990 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1990

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IC'90

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SIGARCH

IC'90: ACM SIGARCH International Conference on Supercomputing

June 11 - 15, 1990

Amsterdam, The Netherlands

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

Hum HGao G(2005)A novel high-speed memory organization for fine-grain multi-thread computingPARLE '91 Parallel Architectures and Languages Europe10.1007/BFb0035095(34-51)Online publication date: 23-Jun-2005
https://doi.org/10.1007/BFb0035095
Ning QGao G(2005)Minimizing loop storage allocation for an argument-fetching dataflow architecture modelPARLE '92 Parallel Architectures and Languages Europe10.1007/3-540-55599-4_112(585-600)Online publication date: 14-Jul-2005
https://doi.org/10.1007/3-540-55599-4_112
Gao GHum HWong Y(2005)An efficient scheme for fine-grain software pipeliningCONPAR 90 — VAPP IV10.1007/3-540-53065-7_147(709-720)Online publication date: 2-Jun-2005
https://doi.org/10.1007/3-540-53065-7_147
Hum Gao (1991)Efficient support of concurrent threads in a hybrid dataflow/von Neumann architectureProceedings of the 1991 Third IEEE Symposium on Parallel and Distributed Processing10.1109/SPDP.1991.218280(190-193)Online publication date: 2-Dec-1991
https://dl.acm.org/doi/10.1109/SPDP.1991.218280
Hum HGao G(1991)A Novel High-Speed Memory Organization for Fine-Grain Multi-Thread ComputingParle ’91 Parallel Architectures and Languages Europe10.1007/978-3-662-25209-3_4(34-51)Online publication date: 1991
https://doi.org/10.1007/978-3-662-25209-3_4
Ungerer TUngerer T(1993)LiteraturverzeichnisDatenflußrechner10.1007/978-3-322-94688-1_9(357-389)Online publication date: 1993
https://doi.org/10.1007/978-3-322-94688-1_9

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