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- Wada KHagihara KTokura N(2007)Area‐time complexity on a vlsi model with boundary layout assumptionSystems and Computers in Japan10.1002/scj.469017060817:6(67-75)Online publication date: 21-Mar-2007
- Kahrs M(2006)Silicon compilation of very high level languageIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.17098711:10(1227-1246)Online publication date: 1-Nov-2006
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