Article

Modeling repeaters explicitly within analytical placement

Authors:

Prashant Saxena,

Bill HalpinAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 699 - 704

https://doi.org/10.1145/996566.996759

Published: 07 June 2004 Publication History

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Abstract

Recent works have shown that scaling causes the number of repeaters to grow rapidly. We demonstrate that this growth leads to massive placement perturbations that break the convergence of today's interleaved placement and repeater insertion flows. We then present two new force models for repeaters targeted towards analytical placement algorithms. Our experiments demonstrate the effectiveness of our repeater modeling technique in preserving placement convergence (often also accompanied by wire-length improvement) at the 45 and 32 nm technology nodes.

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Cited By

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Khatri SShenoy NGiomi JKhouja A(2016)Logic SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-4(27-55)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-4
Papa DMarkov IA. Papa DL. Markov I(2012)Logic Restructuring as an Aid to Physical RetimingMulti-Objective Optimization in Physical Synthesis of Integrated Circuits10.1007/978-1-4614-1356-1_7(105-122)Online publication date: 8-Aug-2012
https://doi.org/10.1007/978-1-4614-1356-1_7
Papa DKrishnaswamy SMarkov IScheffer LPhillips JHu A(2010)SPIREProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133509(373-380)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133509
Show More Cited By

Index Terms

Modeling repeaters explicitly within analytical placement
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

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DAC04: The 41st Annual Design Automation Conference 2004

June 7 - 11, 2004

CA, San Diego, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Khatri SShenoy NGiomi JKhouja A(2016)Logic SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-4(27-55)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-4
Papa DMarkov IA. Papa DL. Markov I(2012)Logic Restructuring as an Aid to Physical RetimingMulti-Objective Optimization in Physical Synthesis of Integrated Circuits10.1007/978-1-4614-1356-1_7(105-122)Online publication date: 8-Aug-2012
https://doi.org/10.1007/978-1-4614-1356-1_7
Papa DKrishnaswamy SMarkov IScheffer LPhillips JHu A(2010)SPIREProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133509(373-380)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133509
Wu HWong M(2009)Incremental improvement of voltage assignmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200915528:2(217-230)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009155
Chen TChakraborty APan DFix L(2008)An integrated nonlinear placement framework with congestion and porosity aware buffer planningProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391651(702-707)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391651
Wu HWong MLevitan S(2007)Improving voltage assignment by outlier detection and incremental placementProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278600(459-464)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278600
Hwang CPedram MHirose F(2006)Timing-driven placement based on monotone cell ordering constraintsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118355(201-206)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118355
Li CKoh CMadden PTang T(2005)Floorplan managementProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120867(349-354)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120867
Goplen BSaxena PSapatnekar SJoyner WMartin GKahng A(2005)Net weighting to reduce repeater counts during placementProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065710(503-508)Online publication date: 13-Jun-2005
https://dl.acm.org/doi/10.1145/1065579.1065710

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