Article

Feedback driven instruction-set extension

Authors:

Michael ThiesAuthors Info & Claims

LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

Pages 126 - 135

https://doi.org/10.1145/997163.997182

Published: 11 June 2004 Publication History

Abstract

Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. Since the extension of an instruction set and its utilization are non-trivial tasks, sophisticated tools have to provide guidance and support during design. Feedback driven optimization allows for the highest level of specialization, but calls for a simulator that is aware of the newly proposed instructions, a compiler that makes use of these instructions without manual intervention, and an application program that is representative for the targeted application domain.In this paper we introduce an approach for the extension of instruction sets that is built around a concise yet powerful processor abstraction. The specification of a processor is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator. A typical design cycle involves the execution of the representative application program, evaluation of performance statistics collected by the simulator, refinement of the processor specification guided by performance statistics, and update of the compiler and simulator according to the refined specification. We demonstrate the usefulness of our novel approach by example of an instruction set for symmetric ciphers.

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Cited By

Funck MHerdt VDrechsler R(2022)Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS54261.2022.9770108(14-19)Online publication date: 6-Apr-2022
https://doi.org/10.1109/DDECS54261.2022.9770108
Jungeblut THübener BPorrmann MRückert U(2013)A systematic approach for optimized bypass configurations for application-specific embedded processorsACM Transactions on Embedded Computing Systems10.1145/2514641.251464513:2(1-25)Online publication date: 30-Sep-2013
https://dl.acm.org/doi/10.1145/2514641.2514645
Jungeblut TPuttmann CDreesen RPorrmann MThies MRückert UKastens U(2010)Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptographyAdvances in Radio Science10.5194/ars-8-295-20108(295-305)Online publication date: 22-Dec-2010
https://doi.org/10.5194/ars-8-295-2010
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Feedback driven instruction-set extension

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cover image ACM Conferences

LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

June 2004

276 pages

ISBN:1581138067

DOI:10.1145/997163

General Chair:
David Whalley
Florida State University
,
Program Chair:
Ron Cytron
Washington University

ACM SIGPLAN Notices Volume 39, Issue 7
LCTES '04
July 2004
265 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/998300
Issue’s Table of Contents

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 June 2004

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LCTES04

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LCTES04: Languages, Compilers, and Tools for Embedded Systems 2004

June 11 - 13, 2004

DC, Washington, USA

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Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

Funck MHerdt VDrechsler R(2022)Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS54261.2022.9770108(14-19)Online publication date: 6-Apr-2022
https://doi.org/10.1109/DDECS54261.2022.9770108
Jungeblut THübener BPorrmann MRückert U(2013)A systematic approach for optimized bypass configurations for application-specific embedded processorsACM Transactions on Embedded Computing Systems10.1145/2514641.251464513:2(1-25)Online publication date: 30-Sep-2013
https://dl.acm.org/doi/10.1145/2514641.2514645
Jungeblut TPuttmann CDreesen RPorrmann MThies MRückert UKastens U(2010)Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptographyAdvances in Radio Science10.5194/ars-8-295-20108(295-305)Online publication date: 22-Dec-2010
https://doi.org/10.5194/ars-8-295-2010
Jungeblut TSievers GPorrmann MRuckert U(2010)Design Space Exploration for Memory Subsystems of VLIW ArchitecturesProceedings of the 2010 IEEE Fifth International Conference on Networking, Architecture, and Storage10.1109/NAS.2010.14(377-385)Online publication date: 15-Jul-2010
https://dl.acm.org/doi/10.1109/NAS.2010.14
Jungeblut TDreesen RPorrmann MThies MRückert UKastens U(2010)A Framework for the Design Space Exploration of Software-Defined Radio ApplicationsMobile Lightweight Wireless Systems10.1007/978-3-642-16644-0_14(148-159)Online publication date: 2010
https://doi.org/10.1007/978-3-642-16644-0_14
Dreesen RJungeblut TThies MPorrmann MKastens URückert U(2009)A Synchronization Method for Register Traces of Pipelined ProcessorsAnalysis, Architectures and Modelling of Embedded Systems10.1007/978-3-642-04284-3_19(207-217)Online publication date: 2009
https://doi.org/10.1007/978-3-642-04284-3_19
Pothineni NKumar APaul K(2008)Exhaustive Enumeration of Legal Custom Instructions for Extensible ProcessorsProceedings of the 21st International Conference on VLSI Design10.1109/VLSI.2008.93(261-266)Online publication date: 4-Jan-2008
https://dl.acm.org/doi/10.1109/VLSI.2008.93
Niemann JLiß CPorrmann MRückert U(2007)A multiprocessor cache for massively parallel soc architecturesProceedings of the 20th international conference on Architecture of computing systems10.5555/1763274.1763281(83-97)Online publication date: 12-Mar-2007
https://dl.acm.org/doi/10.5555/1763274.1763281
Niemann JPuttmann CPorrmann MRückert U(2007)Resource efficiency of the GigaNetIC chip multiprocessor architectureJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2006.10.00753:5-6(285-299)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1016/j.sysarc.2006.10.007
Liu XZhang JCheng X(2007)NISDProceedings of the 3rd international conference on Embedded Software and Systems10.1007/978-3-540-72685-2_26(271-282)Online publication date: 14-May-2007
https://dl.acm.org/doi/10.1007/978-3-540-72685-2_26
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