article

Power and energy reduction via pipeline balancing

Authors:

R. Iris Bahar and

Srilatha ManneAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 29, Issue 2

Pages 218 - 229

https://doi.org/10.1145/384285.379265

Published: 01 May 2001 Publication History

Abstract

Minimizing power dissipation is an important design requirement for both portable and non-portable systems. In this work, we propose an architectural solution to the power problem that retains performance while reducing power. The technique, known as Pipeline Balancing (PLB), dynamically tunes the resources of a general purpose processor to the needs of the program by monitoring performance within each program. We analyze metrics for triggering PLB, and detail instruction queue design and energy savings based on an extension of the Alpha 21264 processor. Using a detailed simulator, we present component and full chip power and energy savings for single and multi-threaded execution. Results show an issue queue and execution unit power reduction of up to 23% and 13%, respectively, with an average performance loss of 1% to 2%.

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Cited By

Pouiklis GSirakoulis G(2016)Clock gating methodologies and toolsInternational Journal of Circuit Theory and Applications10.1002/cta.210744:4(798-816)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1002/cta.2107
Endo FCouroussé DCharles H(2015)Micro-architectural simulation of embedded core heterogeneity with gem5 and McPATProceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2693433.2693440(1-6)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1145/2693433.2693440
Bournoutian GOrailoglu A(2015)Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low PowerArchitecture of Computing Systems – ARCS 201510.1007/978-3-319-16086-3_7(83-95)Online publication date: 11-Mar-2015
https://doi.org/10.1007/978-3-319-16086-3_7
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Power and energy reduction via pipeline balancing

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 29, Issue 2

Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01)

May 2001

262 pages

ISSN:0163-5964

DOI:10.1145/384285

Editor:
Per Stenström
Chalmers Univ. of Technology

Issue’s Table of Contents

ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture
June 2001
289 pages
ISBN:0769511627
DOI:10.1145/379240
Chairman:
Per Stenström
Chalmers Univ. of Technology

Copyright © 2001 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 2001

Published in SIGARCH Volume 29, Issue 2

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Cited By

Pouiklis GSirakoulis G(2016)Clock gating methodologies and toolsInternational Journal of Circuit Theory and Applications10.1002/cta.210744:4(798-816)Online publication date: 1-Apr-2016
https://dl.acm.org/doi/10.1002/cta.2107
Endo FCouroussé DCharles H(2015)Micro-architectural simulation of embedded core heterogeneity with gem5 and McPATProceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2693433.2693440(1-6)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1145/2693433.2693440
Bournoutian GOrailoglu A(2015)Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low PowerArchitecture of Computing Systems – ARCS 201510.1007/978-3-319-16086-3_7(83-95)Online publication date: 11-Mar-2015
https://doi.org/10.1007/978-3-319-16086-3_7
Lukefahr APadmanabha SDas RDreslinski RWenisch TMahlke SAmaral JTorrellas J(2014)Heterogeneous microarchitectures trump voltage scaling for low-power coresProceedings of the 23rd international conference on Parallel architectures and compilation10.1145/2628071.2628078(237-250)Online publication date: 24-Aug-2014
https://dl.acm.org/doi/10.1145/2628071.2628078
Saravanan VAnpalagan AKothari DWoungang IObaidat M(2014)A comparative simulation study on the power---performance of multi-core architectureThe Journal of Supercomputing10.1007/s11227-014-1263-170:1(465-487)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.1007/s11227-014-1263-1
Lukefahr APadmanabha SDas RSleiman FDreslinski RWenisch TMahlke S(2012)Composite CoresProceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2012.37(317-328)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1109/MICRO.2012.37
Ponomarev DKucuk GGhose K(2006)Dynamic Resizing of Superscalar Datapath Components for Energy EfficiencyIEEE Transactions on Computers10.1109/TC.2006.2355:2(199-213)Online publication date: 1-Feb-2006
https://dl.acm.org/doi/10.1109/TC.2006.23
Owahid AJohn E(2023)Instruction Profiling Based Predictive Throttling for Power and PerformanceIEEE Transactions on Computers10.1109/TC.2023.330607972:12(3532-3545)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1109/TC.2023.3306079
Bhattacharjee PTrivedi GMajumder A(2022)On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategiesInternational Journal of Electronics10.1080/00207217.2022.2158493(1-20)Online publication date: 28-Dec-2022
https://doi.org/10.1080/00207217.2022.2158493
Tarsa SChowdhury RSebot JChinya GGaur JSankaranarayanan KLin CChappell RSinghal RWang HManne SHunter HAltman E(2019)Post-silicon CPU adaptation made practical using machine learningProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322267(14-26)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322267
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