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A portable global optimizer and linker

Published: 01 June 1988 Publication History
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  • Abstract

    To reduce complexity and simplify their implementation, most compilers are organized as a set of passes or phases. Each phase performs a particular piece of the compilation process. In an optimizing compiler, the assignment of function and order of application of the phases is a critical part of the design. A particularly difficult problem is the arrangement of the code generation and optimization phases so as to avoid phase ordering problems caused by the interaction of the phases. In this paper, we discuss the implementation of a compiler/linker that has been designed to avoid these problems. The key aspect of this design is that the synthesis phases of the compiler and the system linker share the same intermediate program representation. This results in two benefits. It permits the synthesis phases of the compiler to be performed in any order and repeatedly, thus eliminating potential phase ordering problems. Second, it permits code selection to be invoked at any point during the synthesis phases as well as at link time. The ability to perform code selection at link time presents many opportunities for additional optimizations. Measurements about the effectiveness of using this approach in a C compiler on two different machines are presented.

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    Cited By

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    • (2024)Optimization Algorithm for Link Time Based on Function Reordering2023 8th International Conference on Control, Robotics and Cybernetics (CRC)10.1109/CRC60659.2023.10488559(222-229)Online publication date: 22-Dec-2024
    • (2019)Comparative analysis of simulation system for teaching compilersBizinfo Blace10.5937/bizinfo1902001S10:2(1-23)Online publication date: 2019
    • (2015)Scheduling instruction effects for a statically pipelined processorProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830710(167-176)Online publication date: 4-Oct-2015
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    Published In

    cover image ACM SIGPLAN Notices
    ACM SIGPLAN Notices  Volume 23, Issue 7
    Proceedings of the SIGPLAN '88 conference on Programming language design and implementation
    July 1988
    338 pages
    ISSN:0362-1340
    EISSN:1558-1160
    DOI:10.1145/960116
    Issue’s Table of Contents
    • cover image ACM Conferences
      PLDI '88: Proceedings of the ACM SIGPLAN 1988 conference on Programming language design and implementation
      June 1988
      338 pages
      ISBN:0897912691
      DOI:10.1145/53990
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 01 June 1988
    Published in SIGPLAN Volume 23, Issue 7

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    • (2024)Optimization Algorithm for Link Time Based on Function Reordering2023 8th International Conference on Control, Robotics and Cybernetics (CRC)10.1109/CRC60659.2023.10488559(222-229)Online publication date: 22-Dec-2024
    • (2019)Comparative analysis of simulation system for teaching compilersBizinfo Blace10.5937/bizinfo1902001S10:2(1-23)Online publication date: 2019
    • (2015)Scheduling instruction effects for a statically pipelined processorProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830710(167-176)Online publication date: 4-Oct-2015
    • (2015)Optimizing Transfers of Control in the Static Pipeline ArchitectureACM SIGPLAN Notices10.1145/2808704.275495250:5(1-10)Online publication date: 4-Jun-2015
    • (2015)Optimizing Transfers of Control in the Static Pipeline ArchitectureProceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM10.1145/2670529.2754952(1-10)Online publication date: 4-Jun-2015
    • (2015)Scheduling instruction effects for a statically pipelined processor2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2015.7324557(167-176)Online publication date: Oct-2015
    • (2014)Analyzing and addressing false interactions during compiler optimization phase orderingSoftware—Practice & Experience10.1002/spe.217644:6(643-679)Online publication date: 1-Jun-2014
    • (2013)Improving processor efficiency by statically pipelining instructionsACM SIGPLAN Notices10.1145/2499369.246555948:5(33-44)Online publication date: 20-Jun-2013
    • (2013)Improving processor efficiency by statically pipelining instructionsProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2491899.2465559(33-44)Online publication date: 20-Jun-2013
    • (2013)Improving processor efficiency by statically pipelining instructionsProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2465554.2465559(33-44)Online publication date: 20-Jun-2013
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