Research on Phase Stabilization Algorithm of Femtosecond Timing System

Abstract

This paper presents the design, implementation, and validation of a femtosecond timing system aimed at achieving precise time control and phase synchronization for large particle accelerators. A prototype system utilizing a continuous wave laser was developed, focusing on minimizing timing jitter and long-term phase drift. Key components include an optical delay line for coarse adjustments and a fiber stretcher for fine-tuning, achieving an adjustment precision of 1 femtosecond. The system incorporates a phase detection module with a non-In-phase/Quadrature downconversion approach, enabling high-accuracy phase measurements. A collaborative algorithm was designed to optimize the interplay between the optical delay line and the fiber stretcher, utilizing a proportional-integral-derivative (PID) control algorithm to enhance adjustment precision. A Field Programmable Gate Array (FPGA) served as the core interface converter, facilitating data communication and real-time phase information acquisition. Experimental results demonstrated significant improvements in phase stability, with average phase deviation reduced from 1374.104 fs to 15.782 fs, showcasing the effectiveness of the proposed system in achieving high precision and stability in phase control. This research provides a solid foundation for future advancements in timing systems for high-frequency reference signals.

1. Introduction

As modern large-scale scientific facilities demand increasingly higher temporal precision, the need for femtosecond-level (10⁻¹⁵ s) timing accuracy is particularly urgent in fields such as particle accelerators, ultrafast laser experiments, synchrotron radiation sources, and free-electron laser devices [1]. Large particle accelerator installations require high-precision, high-stability signal distribution systems to transmit the reference signal from the master oscillator to high-frequency local stations located throughout the facility, ensuring that the phases of the high-frequency reference signals received by each local station are mutually locked [2]. Additionally, critical equipment such as particle sources, beam position monitors, and transverse feedback systems also require stable reference signal inputs. Due to the spatial scales of accelerator facilities—ranging from hundreds to thousands of meters—the transmission of reference signals is easily affected by external environmental influences. Therefore, suppressing phase drift and phase jitter as much as possible is essential to meet the specified signal performance requirements. In large particle accelerator facilities currently under construction or planned worldwide, many devices control the particle bunch length to sub-picosecond or even femtosecond levels, such as free-electron laser devices [3,4]. This imposes even higher demands on timing systems, requiring their additional phase drift to reach the femtosecond level [5,6,7].

In high-precision timing technology, the main methods to suppress signal phase drift include temperature control methods, phase averaging methods, and active feedback methods. The temperature control method suppresses phase drift by adjusting the environmental temperature (±0.1 °C to ±0.2 °C) and has been applied in facilities such as the Diamond Light Source [8]. Although effective, it has high maintenance costs and can only achieve picosecond-level phase stability, limiting its application in experiments with extremely short bunches. The phase averaging method uses a short circuit at the end of the cable to form a stable standing wave, achieving stability at the hundreds of femtoseconds level. This method has been applied at Stanford and Fermilab [9]. However, it is susceptible to noise and requires complex configurations and precise adjustments, increasing the difficulty and cost.

The active feedback method suppresses phase drift caused by temperature variations through a negative feedback mechanism and can be categorized into electronic-based and optical-based distribution systems. In electronic-based distribution systems, researchers at the European Organization for Nuclear Research (CERN) developed the White Rabbit system based on the Precision Time Protocol (PTP, IEEE1588) of Synchronous Ethernet, achieving deterministic delay timing triggers [10]. Moreover, the system transmits phase-stable high-frequency reference signals through distributed Direct Digital Synthesizers (DDS). By suppressing phase drift caused by Ethernet delays via a feedback mechanism, the White Rabbit system achieves a long-term signal phase stability of 20 picoseconds [11]. Event timing systems independently developed by Finland’s MRF company and the Shanghai Institute of Applied Physics of the Chinese Academy of Sciences dynamically compensate for temperature changes through optical fiber networks, achieving a long-term signal phase stability of 10 picoseconds [12]. However, the inherent noise of electronic systems limits their precision improvement, making it challenging to achieve stable transmission below the picosecond level.

Optical-based distribution systems currently have two technical approaches that can achieve sub-picosecond to femtosecond-level phase stability. The first approach is based on pulsed mode-locked lasers, detecting delay variations through cross-correlation functions and optical compensation, achieving femtosecond-level precision [13]. This method has been applied in multiple accelerator facilities. However, it is sensitive to external interference and difficult to actively compensate for temperature drift. The second approach is based on continuous-wave lasers, detecting delay variations through the Michelson interferometer method and electronic compensation, achieving a phase stability of 10 femtoseconds [14]. This technology offers advantages such as strong anti-interference capabilities and convenient system setup.

This work focuses on constructing a femtosecond timing system prototype based on continuous-wave lasers. In this system prototype, a high-frequency reference signal phase compensation system based on a PID control algorithm was designed and implemented. The algorithm development and communication between the host computer and the key devices controlling the phase were completed. In the process of achieving communication, an FPGA was innovatively programmed as a critical interface converter. This autonomous development enabled effective communication between the host computer and the optical fiber stretcher, showcasing a novel approach in the integration and application of FPGA technology within the system.

This research achieved phase stability control of the high-frequency reference signal. Under laboratory conditions, the long-term phase drift of the high-frequency reference signal was controlled within 20 femtoseconds (R.M.S.).

2. System Introduction

To achieve phase-stable transmission of high-frequency reference signals over long distances and extended periods, it is essential to precisely control two key technical parameters of the signal distribution system: short-term additional timing jitter and long-term phase drift. Moreover, factors such as temperature fluctuations and mechanical vibrations require careful attention due to their substantial impact on phase stability. In our experimental setup, we implement significant measures to stabilize the environmental temperature, thereby mitigating its influence on phase stability. To counteract the challenges posed by mechanical vibrations, we enclosed the optical fibers in foam boxes, effectively minimizing external disturbances. Furthermore, the power of the laser plays a crucial role in phase stability. In our experiments, we meticulously adjusted the received laser signal power to align precisely within the photodiode’s monotonic linear response region. This adjustment enhances the accuracy of photoelectric conversion, thereby contributing to improved phase stability of the system.

To effectively reduce short-term timing jitter to the desired target, a laser module with a linewidth on the order of kilohertz is selected. This module can generate continuous-wave laser signals at 1560.48 nm, and its wavelength stability can reach an accuracy of 10⁻¹⁰. By modulating the high-frequency reference signal onto this laser carrier, the system’s short-term additional timing jitter can be maintained at the femtosecond level.

To suppress the long-term phase drift of the high-frequency reference signal, it is first necessary to construct an optical fiber network that modulates the high-frequency reference signal onto the laser signal and collects its phase information using the independently developed radio-frequency electronic equipment. This equipment is capable of detecting delay variations at the femtosecond level or even smaller. After collecting the phase information, it is transmitted to a computer for feedback control.

The system design introduces a feedback loop based on a PID (Proportional-Integral-Derivative) control algorithm to calculate the phase compensation feedback value [15]. This feedback value is then converted into control commands for the fiber stretcher and optical delay line, which are transmitted to the corresponding devices. This design ensures that the system’s long-term phase drift is controlled at the femtosecond level, achieving high-precision phase-stable transmission. The system architecture based on the above design is shown in Figure 1. In this figure, AM refers to the Analog Modulator, where the high-frequency reference signal is modulated onto the laser carrier. The ODL, or Optical Delay Line, serves as a device for coarse phase adjustment of the signal.

Phase measurement accuracy is the core foundation of femtosecond timing systems, directly affecting the overall performance and precision of the system. High-precision phase measurement ensures accurate time synchronization, thereby enhancing the reliability and effectiveness of experiments and applications.

The design of the phase detection system down-converts the high-frequency RF signal to an intermediate frequency using non-I/Q sampling and undersampling techniques and removes higher-order harmonic interference in the spectrum through multi-stage CIC filters [16]. To further improve the accuracy of amplitude and phase measurements, the system employs a reference tracking algorithm to compensate for various errors in the sampling clock [17]. This design can achieve high-precision signal processing with lower hardware complexity, reaching femtosecond-level phase measurement.

3. Phase Correction Module Design

3.1. Overall Design

The structure of the phase correction scheme is illustrated in Figure 2, which employs a phase correction solution using optical delay devices. The Optical Delay Line (ODL) is responsible for the coarse adjustments of substantial delays on the order of hundreds of picoseconds, whereas the fiber stretcher is employed for the fine-tuning of minor delays, achieving precisions on the scale of tens of femtoseconds, with an accuracy reaching up to 1 femtosecond.

In the system architecture, the EPICS software system (version 3.15.5) is deployed on a personal computer (PC), functioning to acquire real-time phase information of the high-frequency signal via a network optical fiber from a hub (HUB) [18]. Once this information is obtained, the system calculates the necessary control parameters through an automatic control algorithm and achieves precise control of the optical delay line and the fiber stretcher via data lines. The optical delay line is equipped with a standard RS232 communication interface, allowing for straightforward data exchange between the PC and the device. However, the design of the fiber stretcher employs a relatively rare 20-pin digital input parallel interface, which presents unique challenges for data transmission.

To overcome this challenge and ensure efficient and flexible data transmission, this study introduces the Field Programmable Gate Array (FPGA) technology [19]. The FPGA serves as a core component responsible for interface conversion during the data transmission process. Specifically, the host PC first establishes a communication link with the FPGA via a Universal Asynchronous Receiver-Transmitter (UART) serial connection. Subsequently, the FPGA packages and organizes the data received from the PC.

After completing the packaging and organization of the data, the FPGA further transmits this information to the fiber stretcher in parallel format. This design not only leverages the FPGA’s powerful capabilities in data processing but also effectively resolves the data transmission challenges posed by the fiber stretcher’s specialized interface.

3.2. FPGA Design

For the data interface conversion module, we employ the Xilinx Artix 7 series FPGA (AMD, Santa Clara, CA, USA), specifically the model XC7A35TFGG484-2. The design of the interface conversion module mainly includes a serial data reception module, a data packaging module, a parallel data transmission module, and circuits for clock, power, and reset. The overall block diagram of the FPGA conversion module system is shown in Figure 3, implemented using Verilog.

The serial data reception module implements the UART (Universal Asynchronous Receiver-Transmitter) protocol and is responsible for receiving serial data from the host PC. The primary function of the data packaging module is to merge the received 8-bit wide data units into a 16-bit wide data frame. Finally, the parallel data transmission module is responsible for packaging the formatted 16-bit data frame and efficiently transmitting it via a set of parallel lines.

The workflow is illustrated in Figure 4, detailing the operations of each module. First, a classic edge detection strategy is employed to monitor the transmission start signal, referred to as start_flag. When start_flag is activated, a counter is initiated, and upon reaching a preset value, the uart_done signal is set high, indicating the completion of data reception. In the data packaging module, the primary task is to detect the uart_done signal. When this signal is activated, the module stores the received data. If the uart_done signal is detected as high in two consecutive instances, the module merges these two data units to form a 16-bit data frame. The parallel data transmission module is responsible for monitoring the data_ready signal from the data packaging module. Upon detecting the activation of the data_ready signal, the module sends the data frame to the target device, completing the transmission.

After the complete design, simulation verification of the module is required. Figure 5 presents the verification result waveform of the interface conversion module, from which the specific signal changes during the operational process can be observed.

The module receives continuous serial input signals, with the first received data being the hexadecimal number AB, followed by another hexadecimal number CD. Through the designed algorithms and logic, the module is able to correctly package these two data units, generating a new hexadecimal number CDAB. Subsequently, the module transmits the packaged data to the designated target device. The functionality of the module has been validated through functional simulation.

3.3. Performance Verification of Phase Correction Devices and Phase Detection Modules

Upon completing the design of the FPGA-based interface conversion module, testing of the phase correction device and the phase detection module can commence. The real-time detection accuracy of the high-frequency reference signal’s phase is central to this experiment, while precise phase correction equipment is crucial for ensuring the reliability of the experiment, as its accuracy directly impacts the validity of the results. During the functional testing of the phase correction device, the correctness of the phase detection platform can also be validated, facilitating mutual verification between the two components. This process is vital for ensuring the overall system’s accuracy and provides a solid technical foundation and reliable basis for subsequent experiments.

The functional test algorithm for the optical delay line is set to begin from an initial phase of 0, with a delay increase of 1 picosecond every 2 s until a total delay of 28 picoseconds is reached. For the fiber stretcher’s functional test, the algorithm starts with the phase of the high-frequency reference signal at 0, increasing the delay by 100 femtoseconds every 5 s until it reaches 900 femtoseconds. The test results, as shown in Figure 6, are consistent with expectations.

The testing outcomes demonstrate that the phase correction device can achieve precise control, and the results from both the phase correction and phase detection modules align with the anticipated outcomes. This achievement lays a strong foundation for subsequent experiments, ensuring the accuracy and stability of the system.

4. System Algorithm Design

The host PC retrieves real-time phase information of the high-frequency signal through the EPICS software framework and develops a collaborative control program in the MATLAB (2021b) environment to implement an automatic control algorithm.

In this system, the optical delay line is responsible for coarse adjustments of larger delays in the range of hundreds of picoseconds. However, due to the limited adjustment precision of the optical delay line, we introduced a fiber stretcher for fine-tuning small delays within the femtosecond range, achieving a tuning accuracy of 1 femtosecond.

To ensure the coordinated operation of the two devices, an optimized algorithm process must be designed to effectively coordinate the interaction between the optical delay line and the fiber stretcher. Additionally, a set of automatic control algorithms needs to be developed to achieve precise automated adjustments of the delay, thereby meeting the high-precision delay control objectives of the system.

4.1. Algorithmic Flow

First, the initialization process for the optical delay line and fiber stretcher is executed. Next, real-time phase data of the high-frequency reference signal is obtained through the EPICS channel. Once this phase information is acquired, it is analyzed and evaluated. If the detected real-time phase delay is less than 50 femtoseconds (fs), we will use the fiber stretcher for precise phase control. Conversely, if the phase delay exceeds 50 femtoseconds, the optical delay line will be employed for adjustment. It is important to note that the control amount of the optical delay line is cumulative; thus, while adjusting with the optical delay line, the control amount of the fiber stretcher needs to be reset to zero to prevent interference between the two control methods. The algorithm flowchart is shown in Figure 7.

4.2. Automatic Control Algorithms

We employ a PID algorithm as the core automatic control mechanism in our system, leveraging its longstanding reputation in control engineering for robustness, reliability, and straightforward implementation. Given the demands for high precision in timing systems, particularly in applications like particle accelerators, the PID controller is particularly advantageous due to its ability to automatically fine-tune control parameters. This adaptability ensures stable system outputs, rapid responses, and precise regulation, thereby enhancing overall performance. The design of the PID controller integrates proportional, integral, and derivative strategies to optimize output adjustments.

5. System Testing

5.1. Signal Phase Test Without Automatic Control

A timing system prototype has been developed based on structural divisions, as illustrated in Figure 8. In particular, Figure 8a depicts the physical prototype of the timing system, while Figure 8b presents the schematic representation of the continuous-wave laser unit. The fiber length is 0.5 m, and the frequency of the high-frequency reference signal is 499.8 MHz.

In the absence of the phase correction module and algorithms, the phase delay of the high-frequency reference signal and the ambient temperature over time are shown in Figure 9. From the figure, it can be observed that after 8 h of continuous testing, the temperature fluctuation reached 1 °C, under which the maximum phase offset was 2484.75 fs, with an average offset of 1374.104 fs.

5.2. PID Algorithm Testing

The performance of the PID control algorithm is significantly influenced by its parameter settings, where the choice of parameters directly correlates with the system’s response speed and stability. Inappropriate parameter configurations may lead to excessive oscillations and prolonged response times, adversely affecting control performance. During the parameter optimization process, a step-by-step approach should be adopted. First, the proportional coefficient K_p is determined, setting the integral coefficient K_i and derivative coefficient K_d to zero in this phase, to observe the basic impact of proportional control on system response. Next, the integral coefficient K_i is gradually adjusted starting from a small value to assess its effect on the system’s error accumulation correction capability. Finally, the derivative coefficient K_d is adjusted to optimize the system’s response to rapid changes and reduce overshoot [20,21]. The final selections were K_p = 1, K_i = 0.2, and K_d = 0.

Figure 10 compares the performance of the simple conditional control algorithm with the PID control algorithm. It is evident that without the PID algorithm, the fluctuations in the signal phase were considerable, and the adjustment amplitude was quite pronounced. In contrast, after implementing the PID control algorithm, the signal changes became smoother, and the adjustment process exhibited greater stability.

5.3. System Testing

After enabling the phase correction module and the corresponding PID algorithm, the phase delay of the high-frequency reference signal and the ambient temperature over time are illustrated in Figure 11. The figure indicates that after approximately 8 h of continuous testing, with a temperature fluctuation of 1 °C, the average phase delay is 15.782 fs, and the root mean square (R.M.S.) value of the phase delay is 19.925 fs.

The experimental results demonstrated a significant impact of the phase correction module on the stability of the high-frequency signal phase. Before the activation of the phase correction module, the signal phase exhibited considerable fluctuations and instability. However, once activated, the fluctuations in the signal phase markedly decreased, resulting in significantly improved stability. As shown in

Table 1. Results of experiments.

Phase Offset	Phase Correction Module Not Enable	Enable Phase Correction Module
Average value	1374.104 fs	15.782 fs
RMS	1537.92 fs	19.925 fs
Maximum offset	2484.75 fs	74.85 fs

, the average phase offset of the signal decreased from 1374.104 fs to 15.782 fs, the RMS value reduced from 1537.92 fs to 19.925 fs, and the maximum phase offset dropped from 2484.75 fs to 74.85 fs. This indicates a substantial reduction in the average phase offset and a notable enhancement in signal stability.

6. Conclusions

This paper investigated the design, implementation, and validation processes of a femtosecond timing system, aimed at providing precise time control and phase synchronization solutions for large particle accelerator facilities. By conducting an in-depth analysis of the current state of research and technological challenges in the field, alongside the latest advancements both domestically and internationally, this study constructed a prototype femtosecond timing system based on continuous wave lasers. The design process introduced a collaborative working algorithm for two phase control devices and incorporated a PID control algorithm to optimize adjustment accuracy. Additionally, an FPGA was utilized as the core interface converter, with modular design implemented through Verilog code, facilitating communication with critical devices and ultimately achieving precise phase compensation of the high-frequency reference signal.