#

verilog-simulator

Here is 1 public repository matching this topic...

vb000 / vcs-slave-mode

Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

verilog-simulator shared-object synopsys-vcs

Updated Mar 5, 2020
Makefile

Improve this page

Add a description, image, and links to the verilog-simulator topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the verilog-simulator topic, visit your repo's landing page and select "manage topics."