Ravikumar C.P.

With Moore’s law coming to an inevitable halt, it is apparent that further improvements in price/performance/power will only come through system-level optimizations. With government policies becoming friendly to entrepreneurs due to movements such as “Make in India,” it is all the more important to expose students to new opportunities in system design and manufacturing.  However, system-level design is an interdisciplinary topic and there is no clarity on how it can be included in the existing engineering curriculum. In this paper, I will share my thoughts on the challenges involved and some solutions that are workable. In particular, I will present two ideas that were developed in the industry to help academia in this endeavor. The first is the “Analog System Lab Kit “and the second is an India-wide Student Design Contest sponsored by Texas Instruments. I will share my experiences  in deploying these solutions.

The branch-and-bound algorithm is a powerful pseuo-enumerative technique for solving combinatorial optimization problems. From a partially constructed solution to the optimization problem, the branch-and-bound algorithm computes a bound on the optimal value of the objective function. This bound is used in pruning the search tree if the bound does ot appear to lead to a promising subspace of the total search space. In this paper, we consider a branch-and-bound algorithm for the well-known 0-1 integer linear programming problem (ILP). The 0-1 ILP has many applications in diverse scientific andn engineering applications, and almost any combinatorial optimization problem can be formulated as a 0-1 ILP. When used on large instances of 0-1 ILP, the branch-and-bound algorithm can be computationally intensive. In this paper, we prsent a branch-and-bound algorithm. We have implemented the algorithm on a distributed computing environment consisting of a network of Sun workstations. Experimental results on instances of clique partitioning and set covering problems have shown good speedups in relation to a one-processor solution.

... Nitin Kakkar J-302, PGP Hostels IIM -Bangalore Banerghatta Road, Bangalore – 560076 nitink01@iimb.ernet.in ... The crosstalk noise, crosstalk delay, and delay variation due to IR drop can all be different on a signal x in the two instances of the functional block. ...

ABSTRACT Debugging memory test failures in a system-on-chip design is becoming difficult due to the growing number and sizes of the embedded memories. Low-complexity marching tests, which are ideally suited for production testing, are insufficient for debug and diagnostics. On-chip support for multiple memory test algorithms can be prohibitively expensive. Moreover, memory test engineers would like the flexibility to make small changes to the test sequence. Run-time programmability can be provided through the use of programmable finite state machines and/or microcode in the BIST controllers. Since such controllers have higher area requirement, it is difficult to employ multiple controllers and distribute them geographically on the chip. Therefore, the BIST controller can become a routing hot-spot. Existing memory BIST insertion flows operate on a post-synthesis net-list and ignore the constraints that will be posed by the physical design step that will follow. These constraints include routing congestion and interconnect timing. Similarly, the synthesis of the BIST logic must also address area, test application time and test power constraints. In this paper, we formulate the problem of programmable memory BIST synthesis as an optimization problem and describe an implementation. Results show upto 3X improvement in area and wirelength for industrial designs when a layout-aware flow is used as opposed to manual BIST implementation.

We address the problem of real-time delay-bounded multicasting in wavelength-division multiplexed networks. to avoid problems of synchronization between video and audio frames We describe a technique to synthesize WDM network topologies that can, with a ...

... tech-nique for capacitance estimation based on layout estimation after architectural synthesis was reported [8]. At the behav-ioral level, Potkonjak at al. ... vides a unique solution by producing accurate wire length and capacitance distribution estimation throughout a chip or MCM. ...

IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current drawn from the power supply after the application of a test vector exceeds a threshold value. A ...

Each year, industries compete with one another to recruit the best talent from campuses across India.  The number of students graduating with a bachelors’ or masters’ degree in engineering from India borders around a million/year.  It is difficult to make blanket statements about industry’s expectations from the graduating engineering students due to the variety in the jobs that industries offer. We may classify these jobs into a hierarchy – after-sales services including customer training and support, sales and marketing, testing and validation, design, and manufacturing – where I have listed the jobs in the decreasing order of their total availability.  Due to the wide variation in the nature of these jobs, the skill requirements to perform them can also be expected to vary considerably.  However, there are insufficient attempts to bring clarity to the role for which an engineer is being trained for, resulting in two problems – the problem of not finding the right job (from  a student’s perspective)  and the problem of not finding the right employee (from the company’s perspective).  In this talk, my attempt will be to present the industry’s perspective of recruitment and talent development.  I will discuss the perceived relevance of undergraduate programs, postgraduate programs, Ph.D. programs and training programs.  I will highlight the soft-skills that different industrial sectors look for in new college graduates.  Finally, I will present the skill sets that I believe will be most important from a semiconductor market’s perspective.