SIMD

Stencil computations are the foundation of many large applications in scientific computing. Previous research has shown that several optimization mechanisms, including rectangular blocking and time skewing combined with wavefront-and pipeline-based parallelization, can be used to significantly improve the performance of stencil kernels on multi-core architectures. However, the overall performance impact of these optimizations are difficult to predict due to the interplay of load imbalance, synchronization overhead, and cache locality. This paper presents a detailed performance study of these optimizations by applying them with a wide variety of different configurations, using hardware counters to monitor the efficiency of architectural components, and then developing a set of formulas via regression analysis to model their overall performance impact in terms of the affected hardware counter numbers. We have applied our methodology to three stencil computation kernels, a 7-point jacobi, a 27-point jacobi, and a 7-point Gauss-Seidel computation. Our experimental results show that a precise formula can be developed for each kernel to accurately model the overall performance impact of varying optimizations and thereby effectively guide the performance analysis and tuning of these kernels.

Performance of shared memory processors show negative performance impulses (drawbacks) in certain regions for execution of the basic matrix multiplication algorithm. In this paper we continue with analysis of GPU memory hierarchy and corresponding cache memory organization. We give a theoretical analysis why a negative performance impulse appears for specifics problem sizes. The main reason is the cache storage organization, i.e. the negative performance peak appears caused by mapping of matrix elements onto one cache set, instead of using the whole cache. The obtained experimental results prove our theoretical analysis. We also propose a method to avoid situations where performance drawbacks appear.

In this work we present a programmable and reconfigurable
single instruction multiple data (SIMD) visual processor
based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low level image processing. The cells in the array have a selectable
neighborhood configuration and several registers, which provide
the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS.
The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This
produces a very efficient realization in terms of area: 53.8 GOPS
per mm , which outperforms all results reported so far. We show
that even after normalization, to account for technology scaling,
the proposed architecture is the most efficient among all reported
digital processors. Computation performance to power ratio also
exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported.

At the nanometer scale, the focus of micro-architecture will move from processing to communication. Most general computer architectures to date have been based on a "stored program" paradigm that differentiates between memory and processing and relies on communication over busses and other (relatively) long distance mechanisms.

This paper describes a new parallel architectural system which we have called an MIMD-SIMD hybrid system. As the name implies, MIMD-SIMD hybrid system (also denoted as hybrid system in this paper) is a combination of both SIMD and MIMD systems working concurrently to produce an optimal architecture. This new parallel architecture has the capability of achieving speedup rates more than its corresponding MIMD architecture can achieve alone. We introduce our new SIMD concept and also show the contribution of the SIMD on this hybrid system. We have also developed a general formula for determining the speedup of the hybrid system so that accurate predictions can be made on the performance of the hybrid system. A MIMD-SIMD hybrid system was constructed and was used to implement on a visualization algorithm.

Most contemporary processors offer some version of Single Instruction Multiple Data (SIMD) machinery -vector registers and instructions to manipulate data stored in such registers. The central idea of this paper is to use these SIMD resources to improve the performance of the tail of recursive sorting algorithms. When the number of elements to be sorted reaches a set threshold, data is loaded into the vector registers, manipulated in-register, and the result stored back to memory. Three implementations of sorting with two different SIMD machineries -x86-64's SSE2 and G5's AltiVec -demonstrate that this idea delivers significant speed improvements. The improvements provided are orthogonal to the gains obtained through empirical search for a suitable sorting algorithm . When integrated with the Dynamically Tuned Sorting Library (DTSL) this new code generation strategy reduces the time spent by DTSL up to 22% for moderately-sized arrays, with greater relative reductions for small arrays. Wall-clock performance of d-heaps is improved by up to 39% using a similar technique.

Molecular dynamics (MD) simulations are able to provide a wealth of detailed information about biological systems enabling studies impossible to perform in a laboratory. As such, MD simulations provide insight into important biological processes like protein folding, the mechanism of viral infections, as well as aid modern drug design.

Typical MD simulations require billions of time-steps, at each step evaluating forces between tens to hundreds of thousands of particles. This represents a floating-point bottleneck and suggests that the problem is well-suited for HPC. However, the iterative nature of MD algorithms means that speeding up simulations requires reducing the calculation time of a time-step. As the amount of parallelism is limited by the range of relevant problem sizes, improving absolute performance requires strong scaling. Highly optimized MD codes like GROMACS reach iteration rates in the millisecond range which renders MD strongly latency sensitive and represents unique challenges for efficient parallelization.

The HPC landscape is rapidly changing toward increasing on-chip parallelism as well as heterogeneity through emerging accelerator platforms like GPUs or Intel MIC.
The GROMACS MD package is known for its high performance thanks to hand-tuned SIMD kernels and state-of-the art parallel algorithms. However, making efficient use of modern architectures required a substantial redesign of the previously MPI-only parallelization as well as
entirely new algorithms for wide SIMD units and massive accelerator parallelism.

Here we present our recent work on multi-level heterogeneous parallelization of MD implemented in GROMACS. We have developed new, highly efficient SIMD algorithms for pair force calculation targeting current and future architectures ranging from CPUs to GPUs to FPGAs. Thanks to recent efforts, all compute-intensive code in GROMACS uses SIMD acceleration to maximize single-core CPU performance. OpenMP multithreading allows combining a set of cores with GPUs for node-level heterogeneous parallelization. On the top level, MPI-based neutral-territory domain-decomposition ensures scaling across compute nodes. To maximize the utilization of all compute resources, we employ multi-level, inter- and intra-node dynamic load balancing. The latest version of GROMACS not only provides a dramatic improvement in strong scaling to tens of particles per core at peak, but is able to efficiently utilize all compute units in heterogeneous HPC hardware with an absolute simulation performance between hundreds of nanoseconds to a microsecond a day.

A review of previous array Pascals leads on to a description the
Glasgow Pascal compiler. The compiler is an ISO-Pascal superset
with semantic extensions to translate data parallel statements to
run on multiple SIMD cores. An appendix is given which includes
demonstrations of the tool.

SIMD instructions have been commonly used to accelerate video codecs. The recently introduced HEVC codec like its predecessors is based on the hybrid video codec principle, and, therefore, also well suited to be accelerated with SIMD. In this paper we present the SIMD optimization for the entire HEVC decoder for all major SIMD ISAs. Evaluation has been performed on 14 mobile and PC platforms covering most major architectures released in recent years. With SIMD up to 5× speedup can be achieved over the entire HEVC decoder, resulting in up to 133 fps and 37.8 fps on average on a single core for Main profile 1080p and Main10 profile 2160p sequences, respectively.

We live in a data centric world with the availability of information on web to satisfy the two folded objectives of secured easy access and quick processing. The web solutions, which connect users to information, are well equipped to provide the best facility to its users and web browsers as a platform, are used to deliver services offered by the large and complex applications. JavaScript (JS) is the most popular and pervasive web scripting language because it is supported by all the web browsers. But, new alternatives are always evaluated to overcome its shortcomings. With the advancement in technology, programming languages have also added the new computing strategies. One such introduced by Google is Dart. With the latest set of programming features, it is such a programming language which is designed to utilize direct hardware capabilities just like C/C++ along with maximum utilization of CPU. The idea discussed in this paper is that the use of Dart as a Programming Language wil...

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Jakarta, Oktober 2020

Augmenting a processor with special hardware that is able to apply a Single Instruction to Multiple Data (SIMD) at the same time is a cost effective way of improving processor performance. It also offers a means of improving the ratio of processor performance to power usage due to reduced and more effective data movement and intrinsically lower instruction counts. This paper considers and compares the NEON SIMD instruction set used on the ARM Cortex-A series of RISC processors with the SSE2 SIMD instruction set found on Intel platforms within the context of the Open Computer Vision (OpenCV) library. The performance obtained using compiler auto-vectorization is compared with that achieved using hand-tuning across a range of five different benchmarks and ten different hardware platforms. On the ARM platforms the hand-tuned NEON benchmarks were between 1.05× and 13.88× faster than the auto-vectorized code, while for the Intel platforms the hand-tuned SSE benchmarks were between 1.34× and 5.54× faster.

Inspired by the function, power, and volume of the organic brain, we are developing TrueNorth, a novel modular, non-von Neumann, ultra-low power, compact architecture. TrueNorth consists of a scalable network of neurosynaptic cores, with each core containing neurons, dendrites, synapses, and axons. To set sail for TrueNorth, we developed Compass, a multi-threaded, massively parallel functional simulator and a parallel compiler that maps a network of long-distance pathways in the macaque monkey brain to TrueNorth. We demonstrate near-perfect weak scaling on a 16 rack IBM® Blue Gene®/Q (262144 CPUs, 256 TB memory), achieving an unprecedented scale of 256 million neurosynaptic cores containing 65 billion neurons and 16 trillion synapses running only 388× slower than real time with an average spiking rate of 8.1 Hz. By using emerging PGAS communication primitives, we also demonstrate 2× better real-time performance over MPI primitives on a 4 rack Blue Gene/P (16384 CPUs, 16 TB memory).

"This Contemporary computer systems are multiprocessor or multicomputer machines. Their efficiency depends on good methods of administering the executed works. Fast processing of a parallel application is possible only when its parts are appropriately ordered in time and space. This calls for efficient scheduling policies in parallel computer systems. In this work deterministic problems of scheduling are considered. The classical scheduling theory assumed that the application in any moment of time is executed by only one processor. This assumption has been weakened recently, especially in the context of parallel and distributed computer systems. This monograph is devoted to problems of deterministic scheduling applications (or tasks according to the scheduling terminology) requiring more than one processor simultaneously. We name such applications multiprocessor tasks. In this work the complexity of open multiprocessor task scheduling problems has been established. Algorithms for scheduling multiprocessor tasks on parallel and dedicated processors are proposed. For a special case of applications with regular structure which allow for dividing it into parts of arbitrary size processed independently in parallel, a method of finding optimal scattering of work in a distributed computer system is proposed. The applications with such regular characteristics are called divisible tasks. The concept of a divisible task enables creation of tractable computation models in a wide class of computer architectures such as chains, stars, meshes, hypercubes, multistage networks. Divisible task method gives rise to the evaluation of computer system performance. Examples of such performance evaluation are presented. This work summarizes earlier works of the author as well as contains new original results. Mukul Varshney | Jyotsna | Abhakiran Rajpoot | Shivani Garg""Problems in Task Scheduling in Multiprocessor System"" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-4 , June 2017, URL: http://www.ijtsrd.com/papers/ijtsrd2198.pdf
Article URL: http://www.ijtsrd.com/computer-science/computer-architecture/2198/problems-in-task-scheduling-in-multiprocessor-system/mukul-varshney"

In this paper we present a VLSI architecture, which acts as both a SIMD and a wavefront processor to compute the dynamic time-warping (DTW) algorithm. The DTW algorithm is separated into two independent modules. One is for computing the local distances; the other is for computing the minimum distances. We propose the SIMD and wavefront processor architecture to compute local distance and minimum distance, respectively. Such architecture is well-suited for VLSI and FPGA implementations because of its regular structure and small number of inputs/outputs. Currently, based on FPGA technology, a SIMD-wavefront datapath chip has been designed and implemented for computing the DTW algorithm.

In this paper, we present a new model of a massively parallel single Instruction Multiple Data (SIMD) structure machines in a distributed system. Among the modelled machines, we distinguish the linear, 2D, 3D meshes, pyramidal structures and GPU structure. All these computers are based physically on a multitude of fine grained processing elements (PE) arranged and coupled according to their associated topological pattern. In this model the host is represented by a distributed agent. Each virtual host agent, deployed in a physical computer, manages a local parallel virtual computer composed by a set of virtual processing elements (VPE). Each VPE is represented by a self threaded object. The distributed virtual host agents are interconnected throw a multi agent system platform. This feature allows combining the performances of a set of physical computers to build a high performance massively parallel virtual machine. The developed software is based on a hard kernel of a parallel virtual machine in which we translate all the physical properties of its different components. This kernel is based on an abstract layer which can be easily extended to the other topological structures. To implement a parallel program in the proposed platform, we have developed a new parallel programming language based on XML and its compiler which allow editing, compiling and running parallel programs. To illustrate the performance of this model, we present an example of a parallel program implementation for the edge detection of a brain MRI image presenting pathology.

We present an efficient O( n ) numerical algorithm for first-order approximation of geodesic distances on geometry images, where n is the number of points on the surface. The structure of our algorithm allows efficient implementation on parallel architectures. Two implementations on a SIMD processor and on a GPU are discussed. Numerical results demonstrate up to four orders of magnitude improvement in execution time compared to the state-of-the-art algorithms.

Fog and mobile edge computing is a paradigm that augments resource-scarce mobile devices with resource-rich network servers to enable ubiquitous computing. Smartphone applications rely on code offloading techniques to leverage high-performance computing opportunities available on edge and cloud servers for compute-intensive applications. Mobile (ARM) and edge/cloud (x86) architectures are heterogeneous and necessitate dynamic binary translation for compiled code migration that increases the application execution time. The application execution time and energy consumption should be lesser on the edge/cloud server as compared with the local mobile execution for optimal offload. Multimedia-based applications contain a large set of single instruction multiple data (SIMD) instructions that are compute and resource intensive. However, dynamic binary translation techniques of SIMD instructions lose the parallelism and optimization because of inefficient vector-to-scalar translation. We present a framework for SIMD instruction translation and offloading for mobile devices (SIMDOM) in cloud and edge environments. The SIMDOM framework reduces the execution overhead of migrated vectorized multimedia application by using vector-to-vector instruction mappings. The framework maps and translates ARM SIMD intrinsic instructions to x86 SIMD intrinsic instructions such that an application programmed for the mobile platform can be executed on the cloud server without any modification. The offload decision is based on inputs from the device energy, network, and application profilers. Experiments show that SIMDOM framework provides 84.78%, 3.41%, and 79.93% energy, time, and performance efficiency, respectively, compared with local offload-disabled execution. Compared with compiled code offloading, the SIMDOM framework provides 55.99%, 57.50%, and 96.23% energy, time, and performance efficiency, respectively.

The rapid increase in the performance of graphics hardware, coupled with recent improvements in its programmability, have made graphics hardware a compelling platform for computationally demanding tasks in a wide variety of application domains. In this report, we describe, summarize, and analyze the latest research in mapping general-purpose computation to graphics hardware.We begin with the technical motivations that underlie general-purpose computation on graphics processors (GPGPU) and describe the hardware and software developments that have led to the recent interest in this field. We then aim the main body of this report at two separate audiences. First, we describe the techniques used in mapping general-purpose computation to graphics hardware. We believe these techniques will be generally useful for researchers who plan to develop the next generation of GPGPU algorithms and techniques. Second, we survey and categorize the latest developments in general-purpose application development on graphics hardware.

In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications. This 2-million transistor design combines a reconfigurable array of cells with a RISC processor core and a high bandwidth memory interface. The system architecture, software tools including a scheduler for reconfigurable systems, and performance analysis (with impressive speedups) for target applications are described. RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC

Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.

At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardwarebased BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of selftest signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel softwarebased self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.

Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the various application areas in performance (and resulting power consumption). In this paper, we show that the combination of an SIMD (singleinstruction multiple-data) processor and a general-purpose DSP is very advantageous for the image processing tasks encountered in smart cameras. While the SIMD processor gives the very high performance necessary by exploiting the inherent data parallelism found in the pixel crunching part of the algorithms, the DSP offers a friendly approach to the more complex tasks. The paper continues to motivate that SIMD processors have very convenient scaling properties in silicon, making the complete, SIMD-DSP architecture suitable for different application areas without changing the software suite. Analysis of the changes in power consumption due to scaling shows that for typical image processing tasks, it is beneficial to scale the SIMD processor to use the maximum level of parallelism available in the algorithm if the IC supply voltage can be lowered. If silicon cost is of importance, the parallelism of the processor should be scaled to just reach the desired performance given the speed of the silicon.

The aim of this work is how to speed up the process of the biological (DNA and proteins) sequence comparison process by using a hybrid parallelisation technique of combining different parallel methods. Smith-Waterman algorithm has been known as the most optimal algorithm for doing the sequence comparison. Unfortunately, this algorithm is considered slow due to its quadratic time complexity. Multiple Instruction Multiple Data (MIMD), Single Instruction Multiple Data (SIMD), and Single Program Multiple Data (SPMD) methods were chosen because of their efficiency, wideavailability in off-the-shelf inexpensive machines and simple network distributed systems. Based on the results, the combined (hybrid) algorithm has succeeded in reducing the overall algorithm execution time.

Despite the widespread adoption of parallel operations in contemporary CPU designs, their use has been restricted by a lack of appropriate programming language abstractions and development environments. To fully exploit the SIMD model of computation such operations offer, programmers depend on CPU specific machine code or implementation-dependent libraries. Here we present vector Pascal (VP), a language designed to enable the elegant and efficient expression of SIMD algorithms. VP imports into Pascal abstraction ...

This paper describes an implementation of a novel major line removal hough transform on a new parallel architectural system, Hybrid System. A Hybrid System is a combination of single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) systems processing at the same time. The line removal algorithm, which is used for detecting lines in an image, strips away major lines so that minor lines can become more easily detectable. The algorithm is implemented and evaluated on the hybrid system. Being a new extended architecture, we also established the derivation for the hybrid system speedup. We were able to obtain speedup that surpasses that of MIMD systems with the same number of PCs. In the paper, we also introduce a new SIMD concept.

Design methodologies based on reuse of intellectual property (IP) components critically depend on techniques to protect IP ownership. IP protection is particularly challenging for hardware/software systems, where an IP core runs embedded software: both the software and the core are valuable IP that must be protected.

We present an efficient algorithm for nonlocal image filtering with applications in electron cryomicroscopy. Our denoising algorithm is a rewriting of the recently proposed nonlocal mean filter. It builds on the separable property of neighborhood filtering to offer a fast parallel and vectorized implementation in contemporary shared memory computer architectures while reducing the theoretical computational complexity of the original filter. In practice, our approach is much faster than a serial, non-vectorized implementation and it scales linearly with image size. We demonstrate its efficiency in data sets from Caulobacter crescentus tomograms and a cryoimage containing viruses and provide visual evidences attesting the remarkable quality of the nonlocal means scheme in the context of cryoimaging. With such development we provide biologists with an attractive filtering tool to facilitate their scientific discoveries.

Hierarchical, multiresolution data representations enable interactive analysis and visualization of large-scale simulations. One promising application of these techniques is to store high performance computing simulation output in a hierarchical Z (HZ) ordering that translates data from a Cartesian coordinate scheme to a one-dimensional array ordered by locality at different resolution levels. However, when the dimensions of the simulation data are not an even power of 2, parallel HZ ordering produces sparse memory and network access patterns that inhibit I/O performance. This work presents a new technique for parallel HZ ordering of simulation datasets that restructures simulation data into large (power of 2) blocks to facilitate efficient I/O aggregation. We perform both weak and strong scaling experiments using the S3D combustion application on both Cray-XE6 (65,536 cores) and IBM Blue Gene/P (131,072 cores) platforms. We demonstrate that data can be written in hierarchical, multiresolution format with performance competitive to that of native data-ordering methods.

Performance of shared memory processors show negative performance impulses (drawbacks) in certain regions for execution of the basic matrix multiplication algorithm. In this paper we continue with analysis of GPU memory hierarchy and corresponding cache memory organization. We give a theoretical analysis why a negative performance impulse appears for specifics problem sizes. The main reason is the cache storage organization, i.e. the negative performance peak appears caused by mapping of matrix elements onto one cache set, instead of using the whole cache. The obtained experimental results prove our theoretical analysis. We also propose a method to avoid situations where performance drawbacks appear.

In the present computing landscape, interpreters are in use in a wide range of systems. Recent trends in consumer electronics have created a new category of portable, lightweight software applications. Typically, these applications have fast development cycles and short life spans. They run on a wide range of systems and are deployed in a target independent bytecode format over Internet and cellular networks. Their authors are untrusted third-party vendors, and they are executed in secure managed runtimes or virtual machines. Furthermore, due to security policies or development time constraints, these virtual machines often lack just-in-time compilers and rely on interpreted execution. At the other end of the spectrum, interpreters are also a reality in the field of high-performance computations because of the flexibility they provide.

Software tools are an important part of the programming environment. Perhaps one of the most pervasive type of software tools is the "static analyzer", as exemplified by cross reference listing tools, and call gra h generators. In this paper, we describe an "extensible" static analvsis tool (CESAT P which is based on the use of a data base management system and associated query len&age. The use of the dbms query language allows an virtually unlimited number of tools to be easily constructed, resulting in an "extensible" software tool.

Over the last decade, significant advances have been made in compilation technology for capitalizing on instruction-level parallelism (ILP). The vast majority of ILP compilation research has been conducted in the context of generalpurpose computing, and more specifically the SPEC benchmark suite.

MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution of the famous massively parallel systems proposed at the end of the eighties. We claim that today such a machine may be integrated in a single chip. On one side, new design methodologies such as IP reuse and, on the other side, the possible high level of integration on a chip let us envisage such a revival.

Parallel processing methods are a means to achieve signi®cant speedup of computationally expensive image understanding algorithms, such as those applied to range images. Practical implementations of these algorithms must deal with the problems of selecting an appropriate parallel architecture and mapping the algorithm onto that architecture. The parallel implementation approaches for range image segmentation that are presented here are applicable to many low-level image understanding algorithms in a variety of parallel architectures. An evaluation of initial data distribution is presented to determine whether a square subimage or a striped subimage distribution would result in the greatest overall reduction in execution time for the given range image segmentation problem. Novel implementations that consider each data distribution's treatment of edge pixels in window operations yield a trade-o between the number of data transfers versus the amount of computation. This trade-o is examined both analytically and experimentally. Additionally, using the same initial data distributions, a : S 0 1 6 7 -8 1 9 1 ( 9 9 ) 0 0 0 0 7 -1 technique is introduced for changing the allocation of work to each of the processors to reduce the number of network settings by one half. This technique and the method for determining the better initial data distribution can be used with any machine and any window-based technique that requires a full window to perform image calculations. Comparisons of range image processing algorithms are performed using``pure'' SIMD algorithms,``pure'' MIMD algorithms, and mixed-mode implementations with both SIMD and MIMD elements. Each of these approaches are quantitatively analyzed and compared for implementing the dierent phases of a particular hybrid range segmentation algorithm. Results of this implementation study indicate that quanti®able reductions in execution time result from the proper choice of parallel mode for each portion of the segmentation process. Ó

GPU devices offer great performance when dealing with algorithms that require intense computational resources. A developer can configure the L1 cache memory of the latest GPU Kepler architecture with different cache size and cache set associativity, per Streaming Multiprocessors (SM). The performance of the computation intensive algorithms can be affected by these cache parameters. In this paper, we evaluate the influence of the performance for all possible configurations of L1 cache size and associativity, for dense matrix-matrix multiplication algorithm for various problem sizes. The results show a small impact of various L1 cache memory configurations for the overall performance of the algorithm.