DRAM

The authors discuss the TMS34010, a high-performance 32-bit microprocessor with special instructions and hardware for handling the bit-field data and address manipulations often associated with computer graphics. They give a history of embedded microprocessors and examine the wide range of processors and applications covered by that term. They provide an overview of the internal architecture of the TMS34010 and discuss the choice of feature set in its design. Although it is aimed at graphics systems, the processor's large address reach, bit-field processing, and DRAM (dynamic random-access memory) interface make it suitable for many other embedded processing applications.>

In this paper average power consumption of dram cell designs have been analyzed for the nanometer scale memories. Many modern processors use dram for on chip data and program memory. The major contributor of power in dram is the off state leakage current. Improving the power efficiency of a dram cell is critical for the improvement in average power consumption of the overall system. 3T dram cell, 4T dram and 3T1D DRAM cells are designed with the schematic design technique and their average power consumption are compared using TANNER EDA tool .average power consumption, write access time, read access time and retention time of 4T, 3T dram and 3T1D DRAM cell are simulated and compared on 32 nm technology.

Abstract Flash memories have been the fastest growing among the different semiconductor memory families; their market has reached a size comparable to the DRAM one and it is expected to keep growing in the coming years. The fantastic success of flash memory is ...

For extreme-scale high performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where the DRAM main memory systems account for about 30-50% of a node's overall power consumption. Moreover, as the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, a number of emerging memory technologies - nonvolatile memory (NVM) devices – are being investigated as an alternative for DRAM. Moving forward, these NVM devices may offer a number of solutions for HPC architectures. First, as the name, NVM, implies, these devices retain state without continuous power, which can, in turn, reduce power costs. Second, certain NVM devices can be as dense as DRAM, facilitating more memory capacity in the same physical volume. Finally, NVM, such as contemporary NAND flash memory, can be less expensive than DRAM in terms of cost per bit. Taken together, these benefits can provide opportunities for revolutionizing the design of extreme-scale HPC systems. Researchers are investigating how to integrate these emerging technologies into future extreme-scale HPC systems, and how to expose these capabilities in the software stack and applications. Current results show a number of these strategies may offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output post-processing, such as transaction-based, incremental-checkpointing and in-situ visualization, respectively.

In this work, the potential of Si1-xGex Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of external resistance is observed for Si1-xGex Quantum Well devices, which is attributed to junction induced defects creation at the SiGe/Si buffer layer interface. This highlights the need for a dedicated junction solution in SiGe QW devices. The junction leakages are also investigated, and it is found that Band to Band Tunneling is the dominant mechanism setting the minimum Off-state leakage current. Band to Band Tunneling is increasing when the Ge content is increased, and it may effectively cap the allowed Ge channel content for Low Power Applications. The minimum Off state leakage requirement for DRAM peripheral applications is still obtained for a Ge concentration of 45%.

This paper reports a functional 4F2 DRAM based on a vertical-channel-access-transistor (VCAT). A new core design methodology is applied to accommodate 4F2 cell array, achieving both high performance and small area. The 88Kb DRAM array is fabricated in a 50Mb test chip at 80nm design rule and the measured random cycle time (tRC) and read latency (tRCD) is 31ns and

In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU's data needs, and are mostly oblivious to the main memory. In this paper, we demonstrate that the era of many-core architectures has created new main memory bottlenecks, and mandates a new approach: coordination of cache policy with main memory characteristics. Using the cache for memory optimization purposes, we propose a Virtual Write Queue which dramatically expands the memory controller's visibility of processor behavior, at low implementation overhead. Through memory-centric modification of existing policies, such as scheduled writebacks, this paper demonstrates that performance limiting effects of highly-threaded architectures can be overcome. We show that through awareness of the physical main memory layout and by focusing on writes, both read and write average latency can be shortened, memory power reduced, an...

With the latest developments in VLSI technology, the size of memories is rapidly
growing. The yield criteria and testing problems have become the most critical areas for
memory manufacturing. Traditionally, redundancies are applied so that the faulty cells
can be repairable. Using external memory testers redundancy analysis is becoming slow
as the chip density continues to grow, especially for the system chip with big embedded
memories. This paper presents three redundancy allocation algorithms which can be
implemented on-chip. Out of three algorithms, two are based on the local-bitmap concept:
the local repair-most approach is good for a general spare configuration, and the local
optimization approach has the better repair rate. The essential spare pivoting technique is
proposed to simplify control circuitry.

This paper describes a 16-Gb/s differential bidirectional I/O transceiver cell in an emulated 40nm DRAM process that has a fan-out of four-inverter delay (FO4) of 45ps, resulting in a bit time that is only 1.4 FO4 delays long. The transceiver implements several techniques to ...