Research Interests:
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad,... more
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad,... more
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. appor t de r ech er ch e
In this contribution, we propose an efficient power estima-tion methodology for complex RISC processor-based plat-forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the... more
In this contribution, we propose an efficient power estima-tion methodology for complex RISC processor-based plat-forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evalu-ate accurately the activities used in the related power mod-els. The combination of the two parts above leads to a het-erogeneous power estimation that gives a better trade-off be-tween accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media bench-marks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained pow...
In this contribution, we propose an efficient power estima-tion methodology for complex RISC processor-based plat-forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the... more
In this contribution, we propose an efficient power estima-tion methodology for complex RISC processor-based plat-forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evalu-ate accurately the activities used in the related power mod-els. The combination of the two parts above leads to a het-erogeneous power estimation that gives a better trade-off be-tween accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media bench-marks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained pow...
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad,... more
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. Software Implementation vs. Hardware Implementation:
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad,... more
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad,... more
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et a ̀ la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.
Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms (filtering, correlation, etc.) and their numerous parameters. Having a flexible and pro-grammable system that... more
Nowadays, recent intensive signal processing applications are evolving and are characterized by the diversity of algorithms (filtering, correlation, etc.) and their numerous parameters. Having a flexible and pro-grammable system that adapts to changing and various characteristics of these applications reduces the design cost. In this context, we propose in this paper Generic Massively Parallel architecture (G-MPSoC). G-MPSoC is a System-on-Chip based on a grid of clusters of Hardware and Software Computation Elements with different size, performance, and complexity. It is composed of parametric IP-reused modules: processor, controller, accelerator, memory, interconnection network, etc. to build different architecture configurations. The generic structure of G-MPSoC facilitates its adaptation to the intensive signal processing applications requirements. This paper presents G-MPSoC architecture and details its different components. The FPGA-based implementation and the experimental re...
Research Interests:
Research Interests:
Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designing Multi Processor-based System on Chip. SPMD (Single Program Multiple Data) is a massively parallel execution model based on the assembly of... more
Nowadays, Field Programmable Gate Arrays (FPGAs) platforms offer a high density to allow designing Multi Processor-based System on Chip. SPMD (Single Program Multiple Data) is a massively parallel execution model based on the assembly of a given number of homogeneous Processing Elements (PEs). This model is often relaying on Master/Slaves architecture composed by a Master PE that manages the parallel execution of a set of identical slave PEs. Furthermore, Dynamic Partial Reconfiguration (DPR) feature allows such computing system to be reconfigured on the fly for a given application requirement. Given the growing number of PEs in Master/Slaves architecture, it is difficult to estimate the time of specification and design during the phase of allocation and floorplanning of Partial Reconfigurable Regions (PRRs) because it is still performed manually. In this work, we present AFFORDe, a tool enable to automate the Xilinx DPR flow for SPMD architecture that allows parsing the resource requirements of the static and the dynamically reconfigurable parts to perform an automatic floorplanning. The floorplanning is based on a Heuristic Algorithm for Automatic Floorplanning in SPMD Architectures (HAAFSA). This tool is used to generate a configuration file that allows floorplanning of reconfigurable regions in an automatic way of a given Master/Slaves configuration. Experimental results show the effectiveness of our tool to increase the design productivity for dynamically reconfigurable SPMD-based architecture.
Research Interests:
Research Interests:
Research Interests:
Reconfigurable technology fits for real-time video streaming applications. It is considered as a promising solution due to the offered performance per watt compared to other technologies. Since FPGA evolved, several techniques at... more
Reconfigurable technology fits for real-time video streaming applications. It is considered as a promising solution due to the offered performance per watt compared to other technologies. Since FPGA evolved, several techniques at different design levels starting from the circuit-level up to the system-level were proposed to reduce the power consumption of the FPGA devices. In this paper, we present a flexible parallel hardware-based architecture in conjunction with frequency scaling as a technique for reducing power consumption in video streaming applications. In this work, we derived equations to ease the calculation for the level of parallelism and the maximum depth for the FIFOs used for clock domain crossing. Accordingly, a design space was formed including all the design alternatives for the application. The preferable design alternative is selected in aware of how much hardware it costs and what power reduction goal it can satisfy. We used Xilinx Zynq ZC706 evaluation board to implement two video streaming applications: Video downscaler (1:16) and AES encryption algorithm to verify our approach. The experimental results showed up to 19.6% power reduction for the video downscaler and up to 5.4% for the AES encryption.
Research Interests:
Research Interests: Computer Science, Multimedia, Formal Analysis, Broadcasting, Model Driven Engineering, and 15 moreCase Study, Multicast, New Car Model Design, Synchronous Language, Formal Verification, Digital television, High performance, Distributed Multimedia Applications, Data Processing, Numerical Solution, Real time and Embedded Systems, Streaming Video, Multimedia Application, Structural model, and Modeling and Analysis
ABSTRACT Data-parallel languages support a single instruction flow; the parallelism is expressed atthe instruction level. Actually, data-parallel languages have chosen arrays to support theparallelism. This regular data structure allows a... more
ABSTRACT Data-parallel languages support a single instruction flow; the parallelism is expressed atthe instruction level. Actually, data-parallel languages have chosen arrays to support theparallelism. This regular data structure allows a natural development of regular parallelalgorithms. The implementation of irregular algorithms necessitates a programming effort toproject the irregular data structures onto regular structures. In this article we present thedifferent techniques used to manage...
Research Interests:
This paper presents the design and analysis of a multimedia system-on-chip consisting of the H.264 encoder implemented on a multiprocessor architecture. A model-driven approach is adopted by using the standard MARTE profile of UML. An... more
This paper presents the design and analysis of a multimedia system-on-chip consisting of the H.264 encoder implemented on a multiprocessor architecture. A model-driven approach is adopted by using the standard MARTE profile of UML. An abstract clock analysis is applied to deal with the correctness of the system temporal properties and to find the most suitable execution platform configurations regarding
Research Interests:
ABSTRACT This paper introduces a new flow able to lit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based on iterative refactoring and transformations of the... more
ABSTRACT This paper introduces a new flow able to lit a parallel application onto an FPGA according to the FPGA characteristics such as computing power and IOs. The flow is based on iterative refactoring and transformations of the application. From the resulting application, a VHDL code is generated. This code is finally used to simulate or synthesize the application. Significant experiments have validated the approach.
Research Interests:
We present a methodology to visually model intensive signal processing applications forembedded systems. This methodology is based on the Array-OL language. The idea is to representan application as a graph of dependencies between tasks... more
We present a methodology to visually model intensive signal processing applications forembedded systems. This methodology is based on the Array-OL language. The idea is to representan application as a graph of dependencies between tasks and arrays. It differs from the classicalreactive programming or message passing paradigm. A task may iterate the same code ondifferent patterns tilling its depending arrays. In this case, visual specifications of dependenciesbetween the pattern...
Research Interests:
Embedded system designs and simulations become tedious and time consuming due to the complexity of modern applications. Thus, languages allowing high level description, such as SystemC, are more and more used. We present in this paper a... more
Embedded system designs and simulations become tedious and time consuming due to the complexity of modern applications. Thus, languages allowing high level description, such as SystemC, are more and more used. We present in this paper a new methodology allowing scripting inside SystemC. We integrate both SystemC and Python within a single framework for system designs and simulations called SystemPy. Communication is performed using a Simple Wrapper and an Interface Generator(SWIG). SystemPy allows dynamic IP changes during the simulation. This makes designers able to perform a quick architecture exploration without stopping the simulation process. Steps and performances of our framework are illustrated on mixed SystemC Python system.
Research Interests:
The design of multiprocessor system-on-chip has performance constraints which must be satisfied by the communication architecture. Multistage interconnection networks have been frequently proposed as connection means in classical... more
The design of multiprocessor system-on-chip has performance constraints which must be satisfied by the communication architecture. Multistage interconnection networks have been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts in the semiconductor industry for solving the problems related to on-chip communications. This paper proposes a methodology for the extension of a generic model (GeNoC) describing onchip communications. At the generic level, the topology component and an extended routing function are defined and implemented in the ACL2 theorem proving environment. We achieve the validation of the extended model on a Delta multistage interconnection networks case study. We thus show the utility of the approach to give a more realistic model describing the communication architectures.
ABSTRACT MPSOC integrated a variety of heterogeneous components which require a communication between them. A solution to flexibility and reconfigurability of interconnects is the use of Network on Chip (NoC). These latter are likely... more
ABSTRACT MPSOC integrated a variety of heterogeneous components which require a communication between them. A solution to flexibility and reconfigurability of interconnects is the use of Network on Chip (NoC). These latter are likely proposing efficient solutions with the complex problems of the embedded system integrations. Multistage interconnection networks have been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts as on-chip communication platform. We describe in this paper the design methodology and the implementation of a Delta multistage interconnection network on chip. Also, we propose a flexible and an efficient model of MPSOC architecture based on Delta MIN. Finally, the effectiveness of the proposed design methodology is shown through parallelized applications on MPSoC architecture.
Research Interests:
Research Interests:
Research Interests:
ABSTRACT This paper presents a communication-centric reconfigurable design for FPGA Mezzanine Card (FMC) based I/O system dedicated to several industrial application domains. The introduction of FMC I/O standard has given a new purpose... more
ABSTRACT This paper presents a communication-centric reconfigurable design for FPGA Mezzanine Card (FMC) based I/O system dedicated to several industrial application domains. The introduction of FMC I/O standard has given a new purpose for FPGAs to be used as a communication platform. In fact, FPGAs can be used for more than just computational purpose in order to improve the system performance. Taking into account the features offered by FPGAs and FMCs, such as runtime reconfiguration and modularity, we have redefined the role of these devices to be used as a generic communication-centric platform. A new modular, runtime reconfigurable, Intellectual Property (IP)-based communication system for industrial applications has been designed. The efficiency and the performances of our platform are illustrated through a real industrial use-cases designed using a computationally intensive application and several I/O bus standards.
Research Interests:
Research Interests:
Research Interests:
Modern embedded systems integrated a variety of complex and heterogeneous components communicating with each other at high-speed rates. The interconnection architecture employed in such systems has an important impact to their overall... more
Modern embedded systems integrated a variety of complex and heterogeneous components communicating with each other at high-speed rates. The interconnection architecture employed in such systems has an important impact to their overall performance. Multistage interconnection network has emerged as a promising alternative to ensure communication for multiprocessor system on chips. In this paper, we describe a design methodology of MIN-based
Research Interests:
ABSTRACT Dynamic reconfiguration using FPGAs has been demonstrated to be highly efficient in different application domains. However little has been explored in the avionic communication domain, where halting the system during runtime for... more
ABSTRACT Dynamic reconfiguration using FPGAs has been demonstrated to be highly efficient in different application domains. However little has been explored in the avionic communication domain, where halting the system during runtime for changing the hardware is non-trivial. In this paper we present a runtime reconfigurable architecture using I/O Intellectual Property (IP) cores, used in avionic applications. The system provides a modular I/O interface for communication, using an FPGA Mezzanine Card (FMC). User application can dynamically install and execute the necessary hardware for communication with external avionic sub-systems using FMC. The system thus provides a highly modular and cost effective autonomous solution for an embedded avionic communication system using Dynamic Partial Reconfiguration (DPR). The above described solution has been tested using a Xilinx ML605 prototyping board providing a software interface with a Xilinx Microblaze processor core. The architecture has been evaluated with the JPEG application in terms of area utilization, reconfiguration latency and execution time. The reconfiguration latency can be hidden totally in many cases. While in certain others, the overhead of reconfiguration can be justified by the reduction in the resource utilization.
Research Interests:
Research Interests:
System adaptivity is increasingly demanded in high-performance embedded systems, particularly in multimedia system-on-chip (SoC), owing to growing quality-of-service requirements. This paper presents a reactive control model that has been... more
System adaptivity is increasingly demanded in high-performance embedded systems, particularly in multimedia system-on-chip (SoC), owing to growing quality-of-service requirements. This paper presents a reactive control model that has been introduced in Gaspard, our framework dedicated to SoC hardware/software co-design. This model aims at expressing adaptivity as well as reconfigurability in systems performing data-intensive computations. It is generic enough to be used for description in the different parts of an embedded system, for example, specification of how different data-intensive algorithms can be chosen according to some computation modes at the functional level; and expression of how hardware components can be selected via the usage of a library of intellectual properties according to execution performances. The transformation of this model toward synchronous languages is also presented, in order to allow an automatic code generation usable for formal verification, based ...
Research Interests:
This paper presents an approach for the modeling and formal validation of high-performance systems. The approach relies on the repetitive model of computation used to express the parallelism of such systems within the Gaspard framework,... more
This paper presents an approach for the modeling and formal validation of high-performance systems. The approach relies on the repetitive model of computation used to express the parallelism of such systems within the Gaspard framework, which is dedicated to the codesign of high-performance system-on-chip. The system descriptions obtained with this model are then projected on the synchronous model of computation.
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests:
Research Interests: Computer Science, GPU, Code Generation, OpenCL, MDE, and 5 moreProfiling, Traceability, Source Code, MARTE, and INRIA
AbstractThis paper proposes an efficient Hybrid Level Power Analysis (HLPA) power consumption modeling approach for complex processors. The main challenge for this approach is to achieve a better trade-offs between accuracy and speed in... more
AbstractThis paper proposes an efficient Hybrid Level Power Analysis (HLPA) power consumption modeling approach for complex processors. The main challenge for this approach is to achieve a better trade-offs between accuracy and speed in power modeling ...
Atmospheric contamination by residual hazardous particles remaining on a substrate following removal from the substrate of a layer of material containing such particles is substantially reduced by coating the substrate with certain... more
Atmospheric contamination by residual hazardous particles remaining on a substrate following removal from the substrate of a layer of material containing such particles is substantially reduced by coating the substrate with certain aqueous coating compositions which produce tacky films on drying. For example, the health hazard from airborne asbestos fibers remaining attached to a substrate from which a layer of asbestos-containing material has been removed is substantially reduced by coating the substrate with an aqueous latex composition containing certain carboxylated butadiene styrene polymers.
Research Interests:
Skip to Main Content. Sign In. Please enter a valid username or password. Username Password. Forgot Username or Password. IEEE.org| IEEE Xplore Digital Library| IEEE Standards| IEEE Spectrum| More Sites. Cart(Loading....) Create Account... more
Skip to Main Content. Sign In. Please enter a valid username or password. Username Password. Forgot Username or Password. IEEE.org| IEEE Xplore Digital Library| IEEE Standards| IEEE Spectrum| More Sites. Cart(Loading....) Create Account |Sign In. Xplore. Access provided by: crawler. Sign Out. Browse: Books & eBooks; Conference Publications; Education & Learning; Journals & Magazines; Standards; By Topic Click to expand or collapse browse ...
Research Interests:
Research Interests:
Multistage interconnection network has been very frequently proposed as connection means in classical on-board multiprocessor systems, it promises to be the solution for the interconnection problems. This paper tries to adapt such... more
Multistage interconnection network has been very frequently proposed as connection means in classical on-board multiprocessor systems, it promises to be the solution for the interconnection problems. This paper tries to adapt such networks for embedded system design. Our approach is to analyze the dynamicity of the link permutation of Delta MINs for MPSOC architectures. This paper presents the design methodology and the performance evaluation of delta MINs. SystemC timed simulations of the proposed ...
Research Interests:
Page 1. www.ecsi.org/dasip 2011 Tampere, Finland, November 2-4, 2011 Poster Session Main Track Embedded Systems Security: An Evaluation Methodology Against Side Channel Attacks Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam... more
Page 1. www.ecsi.org/dasip 2011 Tampere, Finland, November 2-4, 2011 Poster Session Main Track Embedded Systems Security: An Evaluation Methodology Against Side Channel Attacks Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin and Maxime Nassar Interfacing and Scheduling Legacy Code within the Canals Framework Andreas Dahlin, Fareed Jokhio, Jérôme Gorin, Johan Lilius and Mickaël Raulet Range-Free Algorithm ...
An MDE Approach for Energy Consumption Estimation in MPSoC Design Chiraz Trabelsi INRIA Lille Nord Europe France chiraz.trabelsi@inria.fr Samy Meftali INRIA Lille Nord Europe France meftali@lifl.fr Rabie Ben Atitallah INRIA Lille Nord... more
An MDE Approach for Energy Consumption Estimation in MPSoC Design Chiraz Trabelsi INRIA Lille Nord Europe France chiraz.trabelsi@inria.fr Samy Meftali INRIA Lille Nord Europe France meftali@lifl.fr Rabie Ben Atitallah INRIA Lille Nord Europe France benatita@lifl.fr ...