FDL

This paper proposes VHDL-AMS syntax extensions that enable descriptions of AMS systems with partial differential equations. We named the extended language VHDL-AMSP. An important specific need for such extensions arises from the well known MEMS modelling difficulties where complex digital and analogue electronics interfaces with distributed mechanical systems. The new syntax allows descriptions of new VHDL-AMS objects, such as partial quantities, spatial coordinates and boundary conditions. Pending the development of a new standard, a suitable pre-processor has been developed to convert VHDL-AMSP into the existing VHDL-AMS 1076.1 standard automatically. The pre-processor allows development of models with partial differential equations using currently available simulators. As an example, a VHDL-AMSP description for the sensing element of a MEMS accelerometer is presented, converted to VHDL-AMS 1076.1 and simulated in SystemVision.

In this article we show how to use the Rialto intermediate language, to capture the semantics of UML behavioral diagrams. The Rialto language has a formal semantics given as structural operational rules and it supports semantic variations. It can be used to uniformly describe the behavior of a combination of several diagrams and as a bridge from UML models to animation and production code.

The UML (Unified Modeling Language), with the en-hancements in UML 2.0, is receiving interest by an increasing number of industrial and academic groups from the EDA, embedded software and hardware sys-tems, who look at it and at its extension mechanisms as a practical ...

Steadily increasing design sizes, make the verification a bo ttleneck in modern design flows of digital hardware and embedded software systems. Up to 75% of the over all design costs are due to the verification task. Formal methods have been proposed to acco mpany commonly used simulation approaches. In this paper we combine property checking and symbolic simu lation to make these techniques applicable to larger designs and to seamlessly integrate fo rmal verification and standard simulation. Our experimental results show a run time gain over standard s ymbolic model checking and SAT- based bounded model checking for certain classes of circuit s and properties.

We present our approach in using SystemC for simulating a custom configurable architecture, MICAS. However, there are certain aspects of the architecture, like configuration specific information or programming interface, which cannot be directly represented using SystemC concepts. Thus, we define a C++-based specification language for MICAS that allows us to specify additional properties of the architecture at simulation level and furthermore, to combine these properties with the SystemC executable specification.

This paper describes a scenario-based methodology for system-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existing model-driven design methodology for embedded systems based on the SystemC UML profile. It allows the designer to functionally validate system components from SystemC UML designs early at high levels of abstraction and without requiring strong skills and expertise on formal methods. A validation tool integrated into an existing model-driven co-design environment to support the proposed scenario-based validation flow is also presented.

This device is designed to cover and prevent a hypodermic needle in a syringe from possibly scratching a person after it has been used and discarded, which will help prevent spread of contagious diseases. Primarily, it consists of a transparent sleeve that receives the barrel of a hypodermic syringe, and after the needle has been used, the sleeve is pushed forward to cover the needle. The sleeve and the barrel of the syringe cooperate with each other to lock in the forward and needle covering position, by having a self-contained locking mechanism.

The purpose of this paper is to provide empirical results from ten diverse implementation approaches for domain-specific languages, but conducted using the same representative language. Comparison shows that these discussed approaches differ in terms of the effort need to implement ...

SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each object instance into a finite state machine; this effectively duplicates (modulo dead code removal) in hardware the methods of a class for each of its instances. We describe an alternative synthesis approach which parallels the software implementation of objects in which instance attribute values are stored in (registers or) memory and routed, on use, to a per-class implementation of methods. Interestingly, this technique can be seen as mapping a class library into an ASIP (application-specific instruction set processor) whose instructions correspond to public methods of the library. The ODETTE-synthesisable OO features correspond to an ASIP architecture with instructions only having direct addressing. We then show how to extend the synthesisable subset of ODETTE to include object instances addressed by pointer...

Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the range of systolic array’s application, making the choice of the best systolic architecture to a given problem a critical task. In this work we investigate the specification and verification of such architectures using rewriting-logic, which provides a high level design framework for architectural exploration. In particular, we show how to use ELAN rewriting system to specify reconfigurable systems which can perform both arithmetic and symbolic computations.

This paper presents Anahita Processor Description Language (APDL) for generation of retargetable processor design tool sets. The emphasis is on the applicability of the generated tools in the design space exploration (DSE) phase of designing a new embedded processor. APDL descriptions can be used for generating cycle-accurate instruction set simulators, assembler/disassembler tools, production quality compilers and architecture verification tools. The paper first investigates the features required for a language to be useful for DSE and then presents APDL constructs along with code samples.

This paper studies and proposes a joint use of SystemC-AMS and HetSC (Heterogeneous SystemC) heterogeneous specification methodologies. This enables an efficient support of a wide range of Models of Computation (MoCs). In this way, SystemC can be used for the complete specification of embedded systems, which are increasingly heterogeneous, since they include the software control part, digital hardware accelerators, the analog front-end, etc. This paper identifies and solves the syntactical and semantical issues involved in the cooperation of the SystemCAMS and HetSC specification methodologies. This includes considering the availability and suitability of the MoC interface facilities provided by both methodologies, especially those of SystemC-AMS, which will be proposed for future standardization. Some practical aspects, such as the compatibility and installation of their respective libraries and the definition of the set of MoCs covered are also dealt with.

The author in his research has focused on real time digital controllers which traditionally are designed as finite state machines or Petri nets. Such controllers can be eectively,modelled with some subset of UML statecharts and next can directly be implemented in programmable logic devices (for example FPGA). This transformation is being realized by a system known as HiCoS (abbreviation comes from Hierarchical Concurrent System) designed and developed at University of Zielona G´ora by the author.

This paper outlines some fundamental concepts for the development of a s ystem design framework based on standard notations and common CASE tools. We describe an environment for HW/SW co-design of embedded systems based on the Unified Modeling Language (UML) and SystemC. Taking advantage from the capabilities provided by widely used UML tools, this environm ent provides code generation for

We present the mathematical formalism and the verification methodology of the contract-based model developed in the framework of the SPEEDS project. SPEEDS aims at developing methods and tools to support ldquospeculative designrdquo, a design methodology in which distributed designers develop different aspects of the overall system, in a concurrent but controlled way. Our generic mathematical model of contract supports this style of development. This is achieved by focusing on behaviors, by supporting the notion of ldquorich componentrdquo where functional and non-functional aspects of the system can be considered and combined, by representing rich components via their set of associated contracts, and by formalizing the process of component composition.

This paper describes a scenario-based methodology for system-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existing model-driven design methodology for embedded systems based on the SystemC UML profile. It allows the designer to functionally validate system components from SystemC UML designs early at high levels of abstraction and without requiring strong skills and expertise on formal methods. A validation tool integrated into an existing model-driven co-design environment to support the proposed scenario-based validation flow is also presented.

... Aquila, Italy Marcello Pecorari,Orazio Raparelli Technolab srl L'Aquila, Italy Igor Melatti, Enrico Tronci Universit`a di Roma “La Sapienza” Rome, Italy Benedetto Intrigila Universit`a di Roma “Tor Vergata” Roma, Italy Abstract We ...