Hardware Software Codesign

We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Math- works’ Simulink c environment,for functional specification and analysis of performance,criteria such as timing (latency and throughput) and power,dissipation. The flow can exploit trade-offs between,software and hardware,as well as between digital and analog implemen- tations, and it can

Due to their complexity, nowadays it is virtually unconceivable to design and implement large digital systems without the use of computer-aided design tools. Many petri net extensions have been proposed aiming at describing hardware characteristics as accurately as possible. Among all petri net extensions developed for use with digital systems, only two of them have nearly all characteristics needed to describe such systems in full. They are place chart nets, and petri nets for embedded systems. Using the latter as an example we discuss some issues that may improve the capability of petri nets in dealing with digital systems.

– One of the most crucial steps in the design of embedded systems is hardware-software partitioning, ie deciding which components of the system should be implemented in hardware and which ones in software. In this paper, different versions of the partitioning problem ...

This work presents Petri nets as an intermediate model for hardware/software codesign. The main reason of using of Petri nets is to provide a model that allows for formal qualitative and quantitative analysis in order to perform hardware/software partitioning. Petri nets as an intermediate model allows one to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper highlights methods of computing load balance, mutual exclusion degree and communication cost of behavioral description in order to perform the initial allocation and the partitioning. This work is also devoted to describing a method for estimating hardware area, and it also presents an overview of the general partitioning method considering multiple software components.

This paper describes a design flow for rapid-prototyping of data-dominated embedded systems. We use The Math- works' Simulink environment for functional specifica- tion and algorithmic analysis. We developed a library of Simulink blocks, each one parameterized by design choi- ces such as implementation (software, analog or digital hardware) and numerical accuracy (resolution, S/N ratio). Each block is equipped with empirical

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

This work presents Petri nets as an intermediate model for hardware/software codesign. The main reason of using of Petri nets is to provide a model that allows for formal qualitative and quantitative analysis in order to perform hardware/software partitioning. Petri nets as an intermediate model allows one to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper highlights methods of computing load balance, mutual exclusion degree and communication cost of behavioral description in order to perform the initial allocation and the partitioning. This work is also devoted to describing a method for estimating hardware area, and it also presents an overview of the general partitioning method considering multiple software components.

Hardware-software codesign has been a research topic since the beginning of this decade (1990s), but only now are structured methods emerging that focus on automating design. Unfortunately, to date most codesign approaches leverage performance from individual hardware and software tools, rather than enforcing a structured integration of hardware and software systems simultaneously. A few frameworks have successfully done this integration

The aim of this paper is to present a communication synthesis approach stated as an allocation problem. In the proposed approach, communication synthesis allows to transform a system composed of processes that communicate via high-level primitives through abstract channels into a set of processes executed by interconnected processors that communicate via signals and share communication control. The proposed communication synthesis approach deals with both protocol selection and interface generation and is based on binding/allocation of communication units. This approach allows a wide design space exploration through automatic selection of communication protocols. We present a new algorithm that performs binding/allocation of communication units. This algorithm makes use of a cost function to evaluate different allocation alternatives. We illustrate through an example the usefulness of the algorithm for allocating automatically different protocols within the same application system.