Aggressive resolution enhancement techniques such as inverse
lithography (ILT) often lead to comp... more Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, non-rectilinear mask shapes which make mask writing extremely slow and expensive. To reduce shot count of complex mask shapes, mask writers allow overlapping shots, due to which the problem of fracturing mask shapes with minimum shot count is NP-hard. The need to correct for e-beam proximity effect makes mask fracturing even more challenging. Although a number of fracturing heuristics have been proposed, there has been no systematic study to analyze the quality of their solutions. In this work, we propose a new method to generate benchmarks with known optimal solutions that can be used to evaluate the suboptimality of mask fracturing heuristics. We also propose a method to generate tight upper and lower bounds for actual ILT mask shapes by formulating mask fracturing as an integer linear program and solving it using branch and price. Our results show that a state-of-the-art prototype [version of] capability within a commercial EDA tool for e-beam mask shot decomposition can be suboptimal by as much as 3.7 for generated benchmarks, and by as much as 3.6 for actual ILT shapes.
In modern SOC implementations, multi-mode
design is commonly used to achieve better circuit perf... more In modern SOC implementations, multi-mode
design is commonly used to achieve better circuit performance
and power across voltage-scaled, “turbo” and other operating
modes. To our knowledge there is no available systematic
analysis or methodology for the selection of associated signoff
modes for multi-mode circuit implementations. In this paper, we
observe significant impacts of signoff mode selection on circuit
area, power and performance. For example, incorrect choice of
signoff voltages for required overdrive frequencies can incur 12%
suboptimality in power or 20% in area. Using the concept of
mode dominance as a guideline, we propose a scalable, modelbased
adaptive search methodology to explore the design space
for signoff mode selection. Our proposed methodology is duty
cycle-aware in its minimization of lifetime energy. Results show
that our proposed methodology provides > 8% improvement
in performance, for given Vdd, area and power constraints,
compared to the traditional “signoff and scale” method. Further,
the signoff modes determined by our methods result in less than
6% overhead in power compared to the optimal signoff modes.
ABSTRACT Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 (see ... more ABSTRACT Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 (see Ref [1] Kahng etal., Proc. DATE, 2009, pp. 423–428) is a widely adopted NoC power and area estimation tool, but its estimation models can have large errors (up to 185%) versus actual implementations. We present ORION3.0, an open-source tool whose parametric and nonparametric modeling methodologies fundamentally differ from ORION2.0 logic template-based approaches in that the estimation models are derived from actual physical implementation data. When compared with actual implementations, ORION3.0 models achieve average estimation errors of no more than 9.3% across microarchitecture, implementation, and operational parameters as well as multiple router RTL generators. A comprehensive suite of these methodologies has been implemented in ORION3.0 (see Ref [2] Available online: http://vlsicad.ucsd.edu/ORION3/.
Proc. System-Level Interconnect Prediction, Jun 1, 2014
Electromigration (EM) is a growing reliability
concern in sub-22nm technology. Design teams must... more Electromigration (EM) is a growing reliability
concern in sub-22nm technology. Design teams must apply
guardbands to meet EM lifetime requirements, at the cost
of performance and power. However, EM lifetime analysis
cannot ignore front-end reliability mechanisms such as
bias temperature instability (BTI). Although the gate delay
degradation due to BTI can be compensated by adaptive
voltage scaling (AVS), any elevated supply voltage will accelerate
EM degradation and reduce lifetime. Since the degradation
of BTI is front-loaded, AVS can increase electrical stress on
metal wires relatively early during IC lifetime, which can
significantly decrease electromigration reliability. In this paper,
we study the “chicken-egg” interlock among BTI, AVS and
EM and quantify timing and power costs of meeting EM
lifetime requirements with full consideration of BTI and AVS
mechanisms. By applying existing statistical and physical EM
models, we demonstrate that without such considerations,
the inaccuracy (reduction) of EM lifetime due to improper
guardband against BTI at signoff can be as high as 30% in
a 28nm FDSOI foundry technology. Furthermore, we provide
signoff guidelines which suggest that the lifetime penalty can
be compensated by paying a penalty of up to 1.6% in area and
6% in power. We also demonstrate that suboptimal choice of
voltage step size and scheduling strategy can result in up to 1.5
years of decreased EM lifetime.
A well-known recipe for reducing mask cost component in product development is to place non-redun... more A well-known recipe for reducing mask cost component in product development is to place non-redundant elements of layout databases related to multiple products on one reticle plate [1,2]. Such reticles are known as multi-product, multi-layer, or, in general, multi-IP masks. The composition of the mask set should minimize not only the layout placement cost, but also the cost of the manufacturing process, design flow setup, and product design and introduction to market. An important factor is the quality check which should be expeditious and enable thorough visual verification to avoid costly modifications once the data is transferred to the mask shop. In this work, in order to enable the layer placement and quality check procedure, we proposed an algorithm where mask layers are first lined up according to the price and field tone [3]. Then, depending on the product die size, expected fab throughput, and scribeline requirements, the subsequent product layers are placed on the masks with different grades. The actual reduction of this concept to practice allowed us to understand the tradeoffs between the automation of layer placement and setup related constraints. For example, the limited options of the numbers of layer per plate dictated by the die size and other design feedback, made us consider layer pairing based not only on the final price of the mask set, but also on the cost of mask design and fab-friendliness. We showed that it may be advantageous to introduce manual layer pairing to ensure that, e.g., all interconnect layers would be placed on the same plate, allowing for easy and simultaneous design fixes. Another enhancement was to allow some flexibility in mixing and matching of the layers such that non-critical ones requiring low mask grade would be placed in a less restrictive way, to reduce the count of orphan layers. In summary, we created a program to automatically propose and visualize shuttle mask architecture for design verification, with enhancements to due to the actual application of the code.
2009 Design, Automation & Test in Europe Conference & Exhibition, 2009
Abstract As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the s... more Abstract As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION ...
Aggressive resolution enhancement techniques such as inverse
lithography (ILT) often lead to comp... more Aggressive resolution enhancement techniques such as inverse lithography (ILT) often lead to complex, non-rectilinear mask shapes which make mask writing extremely slow and expensive. To reduce shot count of complex mask shapes, mask writers allow overlapping shots, due to which the problem of fracturing mask shapes with minimum shot count is NP-hard. The need to correct for e-beam proximity effect makes mask fracturing even more challenging. Although a number of fracturing heuristics have been proposed, there has been no systematic study to analyze the quality of their solutions. In this work, we propose a new method to generate benchmarks with known optimal solutions that can be used to evaluate the suboptimality of mask fracturing heuristics. We also propose a method to generate tight upper and lower bounds for actual ILT mask shapes by formulating mask fracturing as an integer linear program and solving it using branch and price. Our results show that a state-of-the-art prototype [version of] capability within a commercial EDA tool for e-beam mask shot decomposition can be suboptimal by as much as 3.7 for generated benchmarks, and by as much as 3.6 for actual ILT shapes.
In modern SOC implementations, multi-mode
design is commonly used to achieve better circuit perf... more In modern SOC implementations, multi-mode
design is commonly used to achieve better circuit performance
and power across voltage-scaled, “turbo” and other operating
modes. To our knowledge there is no available systematic
analysis or methodology for the selection of associated signoff
modes for multi-mode circuit implementations. In this paper, we
observe significant impacts of signoff mode selection on circuit
area, power and performance. For example, incorrect choice of
signoff voltages for required overdrive frequencies can incur 12%
suboptimality in power or 20% in area. Using the concept of
mode dominance as a guideline, we propose a scalable, modelbased
adaptive search methodology to explore the design space
for signoff mode selection. Our proposed methodology is duty
cycle-aware in its minimization of lifetime energy. Results show
that our proposed methodology provides > 8% improvement
in performance, for given Vdd, area and power constraints,
compared to the traditional “signoff and scale” method. Further,
the signoff modes determined by our methods result in less than
6% overhead in power compared to the optimal signoff modes.
ABSTRACT Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 (see ... more ABSTRACT Networks-on-Chip (NoCs) are increasingly used in many-core architectures. ORION2.0 (see Ref [1] Kahng etal., Proc. DATE, 2009, pp. 423–428) is a widely adopted NoC power and area estimation tool, but its estimation models can have large errors (up to 185%) versus actual implementations. We present ORION3.0, an open-source tool whose parametric and nonparametric modeling methodologies fundamentally differ from ORION2.0 logic template-based approaches in that the estimation models are derived from actual physical implementation data. When compared with actual implementations, ORION3.0 models achieve average estimation errors of no more than 9.3% across microarchitecture, implementation, and operational parameters as well as multiple router RTL generators. A comprehensive suite of these methodologies has been implemented in ORION3.0 (see Ref [2] Available online: http://vlsicad.ucsd.edu/ORION3/.
Proc. System-Level Interconnect Prediction, Jun 1, 2014
Electromigration (EM) is a growing reliability
concern in sub-22nm technology. Design teams must... more Electromigration (EM) is a growing reliability
concern in sub-22nm technology. Design teams must apply
guardbands to meet EM lifetime requirements, at the cost
of performance and power. However, EM lifetime analysis
cannot ignore front-end reliability mechanisms such as
bias temperature instability (BTI). Although the gate delay
degradation due to BTI can be compensated by adaptive
voltage scaling (AVS), any elevated supply voltage will accelerate
EM degradation and reduce lifetime. Since the degradation
of BTI is front-loaded, AVS can increase electrical stress on
metal wires relatively early during IC lifetime, which can
significantly decrease electromigration reliability. In this paper,
we study the “chicken-egg” interlock among BTI, AVS and
EM and quantify timing and power costs of meeting EM
lifetime requirements with full consideration of BTI and AVS
mechanisms. By applying existing statistical and physical EM
models, we demonstrate that without such considerations,
the inaccuracy (reduction) of EM lifetime due to improper
guardband against BTI at signoff can be as high as 30% in
a 28nm FDSOI foundry technology. Furthermore, we provide
signoff guidelines which suggest that the lifetime penalty can
be compensated by paying a penalty of up to 1.6% in area and
6% in power. We also demonstrate that suboptimal choice of
voltage step size and scheduling strategy can result in up to 1.5
years of decreased EM lifetime.
A well-known recipe for reducing mask cost component in product development is to place non-redun... more A well-known recipe for reducing mask cost component in product development is to place non-redundant elements of layout databases related to multiple products on one reticle plate [1,2]. Such reticles are known as multi-product, multi-layer, or, in general, multi-IP masks. The composition of the mask set should minimize not only the layout placement cost, but also the cost of the manufacturing process, design flow setup, and product design and introduction to market. An important factor is the quality check which should be expeditious and enable thorough visual verification to avoid costly modifications once the data is transferred to the mask shop. In this work, in order to enable the layer placement and quality check procedure, we proposed an algorithm where mask layers are first lined up according to the price and field tone [3]. Then, depending on the product die size, expected fab throughput, and scribeline requirements, the subsequent product layers are placed on the masks with different grades. The actual reduction of this concept to practice allowed us to understand the tradeoffs between the automation of layer placement and setup related constraints. For example, the limited options of the numbers of layer per plate dictated by the die size and other design feedback, made us consider layer pairing based not only on the final price of the mask set, but also on the cost of mask design and fab-friendliness. We showed that it may be advantageous to introduce manual layer pairing to ensure that, e.g., all interconnect layers would be placed on the same plate, allowing for easy and simultaneous design fixes. Another enhancement was to allow some flexibility in mixing and matching of the layers such that non-critical ones requiring low mask grade would be placed in a less restrictive way, to reduce the count of orphan layers. In summary, we created a program to automatically propose and visualize shuttle mask architecture for design verification, with enhancements to due to the actual application of the code.
2009 Design, Automation & Test in Europe Conference & Exhibition, 2009
Abstract As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the s... more Abstract As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION ...
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lithography (ILT) often lead to complex, non-rectilinear mask
shapes which make mask writing extremely slow and expensive. To reduce shot count of complex mask shapes, mask writers allow overlapping shots, due to which the problem of fracturing mask shapes with minimum shot count is NP-hard. The need to correct for e-beam proximity effect makes mask fracturing even more challenging. Although a number of fracturing heuristics have been proposed, there has been no systematic study to analyze the quality of their solutions. In this work, we propose a new method to generate
benchmarks with known optimal solutions that can be used to
evaluate the suboptimality of mask fracturing heuristics. We also propose a method to generate tight upper and lower bounds for actual ILT mask shapes by formulating mask fracturing as an integer linear program and solving it using branch and price. Our results show that a state-of-the-art prototype [version of] capability within a commercial EDA tool for e-beam mask shot decomposition can be suboptimal by as much as 3.7 for generated benchmarks, and by as much as 3.6 for actual ILT shapes.
design is commonly used to achieve better circuit performance
and power across voltage-scaled, “turbo” and other operating
modes. To our knowledge there is no available systematic
analysis or methodology for the selection of associated signoff
modes for multi-mode circuit implementations. In this paper, we
observe significant impacts of signoff mode selection on circuit
area, power and performance. For example, incorrect choice of
signoff voltages for required overdrive frequencies can incur 12%
suboptimality in power or 20% in area. Using the concept of
mode dominance as a guideline, we propose a scalable, modelbased
adaptive search methodology to explore the design space
for signoff mode selection. Our proposed methodology is duty
cycle-aware in its minimization of lifetime energy. Results show
that our proposed methodology provides > 8% improvement
in performance, for given Vdd, area and power constraints,
compared to the traditional “signoff and scale” method. Further,
the signoff modes determined by our methods result in less than
6% overhead in power compared to the optimal signoff modes.
concern in sub-22nm technology. Design teams must apply
guardbands to meet EM lifetime requirements, at the cost
of performance and power. However, EM lifetime analysis
cannot ignore front-end reliability mechanisms such as
bias temperature instability (BTI). Although the gate delay
degradation due to BTI can be compensated by adaptive
voltage scaling (AVS), any elevated supply voltage will accelerate
EM degradation and reduce lifetime. Since the degradation
of BTI is front-loaded, AVS can increase electrical stress on
metal wires relatively early during IC lifetime, which can
significantly decrease electromigration reliability. In this paper,
we study the “chicken-egg” interlock among BTI, AVS and
EM and quantify timing and power costs of meeting EM
lifetime requirements with full consideration of BTI and AVS
mechanisms. By applying existing statistical and physical EM
models, we demonstrate that without such considerations,
the inaccuracy (reduction) of EM lifetime due to improper
guardband against BTI at signoff can be as high as 30% in
a 28nm FDSOI foundry technology. Furthermore, we provide
signoff guidelines which suggest that the lifetime penalty can
be compensated by paying a penalty of up to 1.6% in area and
6% in power. We also demonstrate that suboptimal choice of
voltage step size and scheduling strategy can result in up to 1.5
years of decreased EM lifetime.
lithography (ILT) often lead to complex, non-rectilinear mask
shapes which make mask writing extremely slow and expensive. To reduce shot count of complex mask shapes, mask writers allow overlapping shots, due to which the problem of fracturing mask shapes with minimum shot count is NP-hard. The need to correct for e-beam proximity effect makes mask fracturing even more challenging. Although a number of fracturing heuristics have been proposed, there has been no systematic study to analyze the quality of their solutions. In this work, we propose a new method to generate
benchmarks with known optimal solutions that can be used to
evaluate the suboptimality of mask fracturing heuristics. We also propose a method to generate tight upper and lower bounds for actual ILT mask shapes by formulating mask fracturing as an integer linear program and solving it using branch and price. Our results show that a state-of-the-art prototype [version of] capability within a commercial EDA tool for e-beam mask shot decomposition can be suboptimal by as much as 3.7 for generated benchmarks, and by as much as 3.6 for actual ILT shapes.
design is commonly used to achieve better circuit performance
and power across voltage-scaled, “turbo” and other operating
modes. To our knowledge there is no available systematic
analysis or methodology for the selection of associated signoff
modes for multi-mode circuit implementations. In this paper, we
observe significant impacts of signoff mode selection on circuit
area, power and performance. For example, incorrect choice of
signoff voltages for required overdrive frequencies can incur 12%
suboptimality in power or 20% in area. Using the concept of
mode dominance as a guideline, we propose a scalable, modelbased
adaptive search methodology to explore the design space
for signoff mode selection. Our proposed methodology is duty
cycle-aware in its minimization of lifetime energy. Results show
that our proposed methodology provides > 8% improvement
in performance, for given Vdd, area and power constraints,
compared to the traditional “signoff and scale” method. Further,
the signoff modes determined by our methods result in less than
6% overhead in power compared to the optimal signoff modes.
concern in sub-22nm technology. Design teams must apply
guardbands to meet EM lifetime requirements, at the cost
of performance and power. However, EM lifetime analysis
cannot ignore front-end reliability mechanisms such as
bias temperature instability (BTI). Although the gate delay
degradation due to BTI can be compensated by adaptive
voltage scaling (AVS), any elevated supply voltage will accelerate
EM degradation and reduce lifetime. Since the degradation
of BTI is front-loaded, AVS can increase electrical stress on
metal wires relatively early during IC lifetime, which can
significantly decrease electromigration reliability. In this paper,
we study the “chicken-egg” interlock among BTI, AVS and
EM and quantify timing and power costs of meeting EM
lifetime requirements with full consideration of BTI and AVS
mechanisms. By applying existing statistical and physical EM
models, we demonstrate that without such considerations,
the inaccuracy (reduction) of EM lifetime due to improper
guardband against BTI at signoff can be as high as 30% in
a 28nm FDSOI foundry technology. Furthermore, we provide
signoff guidelines which suggest that the lifetime penalty can
be compensated by paying a penalty of up to 1.6% in area and
6% in power. We also demonstrate that suboptimal choice of
voltage step size and scheduling strategy can result in up to 1.5
years of decreased EM lifetime.