Debora Matos

The cores of a System-on-Chip (SoC) connected by Networks-on-Chip (NoCs) need interfaces to properly send and receive packets. However, in this interfacing, different situations can occur when heterogeneous cores are applied. Applications may require, for example, an irregular traffic behavior or present a large bandwidth variation. These situations may lead to problems in data synchronization. In this paper we show

NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. The situation worsens whenever the application changes its communication pattern, i.e., a portable phone downloads a new service. The buffer's depth is an important resource to assure performance, and has a great impact on power. In this paper we propose the use of a reconfigurable router, where the buffers are dynamically allocated to increase router efficiency in a NoC, even under rather different communication loads. The reconfigurable router allows up to 52% power savings, while maintain the same performance of the homogeneous original router with roughly the same area.

In real applications there are different communication needs among the cores. When NoCs are the means to interconnect the cores, the use of some techniques to optimize the communication are indispensable. From the performance point of view, large buffer sizes ensure performance during different applications execution, but unfortunately, these same buffers are the main responsible for the router total power

MPSoCs systems are composed of heterogeneous cores, and for this reason, the cores can present different bandwidth, different clock domains or still they can require an irregular traffic behavior. When networks-on-chip (NoCs) are used to connect these cores, one very often needs some synchronization solution, and due to the mentioned problems, this might be required for synchronous or asynchronous NOCs. In this paper we show a network interface (NI) with a synchronizer wrapper solution. We verified its applicability for different channel widths and buffer depths of a NoC. These network interfaces were used to connect a H.264 decoder and the simulation results demonstrate that the wrapper provides a reliable synchronization solution, and does not compromise the latency of the network. These interfaces have been successfully implemented in a 0.18um CMOS technology.

In a NoC, the amount of buffers allocated to each communication channel has a significant impact on performance and power consumption. Moreover, since there will be changes in the application communication pattern, or even because a new application is loaded in a SoC, a design based on the worst case scenario will probably either oversize buffers, with obvious power implications,

Network-on-chip (NoC) designs are based on a compromise among latency, power dissipation, or energy, and the balance is usually defined at design time. However, setting all parameters, such as buffer size, at design time can cause either excessive power dissipation (originated by router under utilization), or a higher latency. The situation worsens whenever the application changes its communication pattern, e.g., a portable phone downloads a new service. Large buffer sizes can ensure performance during the execution of different applications, but unfortunately, these same buffers are mainly responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case latency incurs extra dissipation for the mean case, which is much more frequent. In this paper we propose the use of a reconfigurable router, where the buffer slots are dynamically allocated to increase router efficiency in an NoC, even under rather different communication loads. In the proposed architecture, the depth of each buffer word used in the input channels of the routers can be reconfigured at run time. The reconfigurable router allows up to 52% power savings, while maintaining the same performance as that of a homogeneous router, but using a 64% smaller buffer size.

A Network-on-Chip with large FIFO size ensures performance during the execution of different traffic flow, but unfortunately, these same buffers are the main responsible for the router total power dissipation. Another aspect is that by sizing buffers to reach higher throughput incurs in extra dissipation for the mean case, which is much more frequent. In this paper we propose the use of an adaptive router with a mechanism that, using a flow sensor, verifies during run time the behavior of the data traffic. From the observability of the data flow, the system uses a control equation that adapts itself to provide an appropriate buffer depth for each channel to sustain performance with minimum power dissipation. As applications show different traffic behavior at run-time, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was 75% lower and throughput was increased 4.6 times to Xbox application, for the same buffer depth. Moreover, the adaptive router allows up to 28% power savings, while maintain the same performance of the equivalent homogeneous router.

The amount of buffers allocated to each NoC channel has a significant performance and power consumption impact. Moreover, when a NoC-based application could present changes in the communication pattern, or when a new application could be loaded in a SoC, a NoC design based on the worst case scenario probably will present oversize buffers. Besides, it will cause obvious power implications, or the performance will be compromised, since not enough buffers will be used. A runtime mechanism is required to automatically adapt the buffer size as a function of the actual communication pattern. This paper proposes a control mechanism to resize the buffer of an adaptive router, which is able to monitor the traffic behavior, and change the buffer depth of each channel at runtime. Besides, the dynamic configuration of the buffer depth is done without any pause or interruption in the system. As applications show different traffic behavior at runtime, this solution allows one to obtain gains in throughput and latency under rather different communication loads, since the buffers slots are dynamically allocated to increase router efficiency in the NoC. With the proposed architecture the latency was approximately 80% lower and throughput was increased 2 times, on average, for the same buffer depth. Moreover, the adaptive router allows up to 30% power savings, while maintain the same performance of the equivalent homogeneous router.

There are many examples in the literature of applications that show different communication needs within a MPSoC. Very often cores interconnected through a Network-on-Chip have routers containing different buffers size, with different clock speed requirements. In this context, we are proposing a dynamic reconfigurable router for a NoC. With the proposed architecture it is possible to reconfigure the depth of each FIFO of the channel inside the routers. It allows more reusability in the NoC since the FIFO depth in the channels can be defined in accordance with the application. Besides, a buffer that is not used by its own channel can be used by others channel, reducing the power consumption.