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    G. Tassielli

    The trigger system for the Barrel Muon Spectrometer of the ATLAS experiment at LHC will be realized with 1116 Resistive Plate Chambers1 (RPC) units for a total surface of about 4000 m2. The difficulty in accessing the apparatus after the... more
    The trigger system for the Barrel Muon Spectrometer of the ATLAS experiment at LHC will be realized with 1116 Resistive Plate Chambers1 (RPC) units for a total surface of about 4000 m2. The difficulty in accessing the apparatus after the installation has been completed demands a rigorous quality control (Quality Assurance) for each detector. To achieve this task three different
    ABSTRACT The counting of the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Although this technique features a number of advantages, the bottleneck for its... more
    ABSTRACT The counting of the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Although this technique features a number of advantages, the bottleneck for its implementation is represented by the difficulties in realizing a low cost, high-speed electronic interface. In fact, typical time separation between each ionization act in a helium-based gas mixture is from a few ns to a few tens of ns. Thus the read-out interface has to be able to process such a high-speed signals. It will be demonstrated that a read-out channel composed of a fast, large bandwidth preamplifier and of a large conversion rate Analog-to-Digital converter fullfil all the requirements for cluster counting. The recent scaled CMOS integrated circuit technologies allows to realize such a low-cost high-speed front-end, opening the possibility of realizing efficient cluster-counter-based detectors. In this paper, a CMOS 0.13 mum integrated readout circuit, including a fast preamplifier (with a -3B bandwidth of 500 MHz) and lGS/s-6bit ADC is designed for the central tracker of a future collider (ILC, super-B). The performance and the design issues associated to this architecture are discussed.
    ABSTRACT We developed a high performance full chain for drift chamber signals processing. The Front End electronics is a multistage amplifier board based on high performance commercial devices. In addition a fast readout algorithm for... more
    ABSTRACT We developed a high performance full chain for drift chamber signals processing. The Front End electronics is a multistage amplifier board based on high performance commercial devices. In addition a fast readout algorithm for Cluster Counting and Timing purposes has been implemented on a Xilinx-Virtex 4 core FPGA. The algorithm analyzes and stores data coming from a Helium based drift tube and represents the outcome of balancing between efficiency and high speed performance.